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llvm-6502/test/MC/ARM/simple-fp-encoding.s

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Use ARM-style comments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117955 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 21:16:39 +00:00
@ RUN: llvm-mc -mcpu=cortex-a8 -triple armv7-apple-darwin -show-encoding < %s | FileCheck %s
Some instructions end with an "ls" prefix, but it doesn't indicate that they are conditional. Check for those instructions explicitly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117747 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 23:50:21 +00:00
Use ARM-style comments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117955 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 21:16:39 +00:00
@ CHECK: vadd.f64 d16, d17, d16 @ encoding: [0xa0,0x0b,0x71,0xee]
Some instructions end with an "ls" prefix, but it doesn't indicate that they are conditional. Check for those instructions explicitly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117747 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 23:50:21 +00:00
vadd.f64 d16, d17, d16
Improve handling of #-0 offsets for many more pre-indexed addressing modes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138754 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-29 19:36:44 +00:00
Use ARM-style comments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117955 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 21:16:39 +00:00
@ CHECK: vadd.f32 s0, s1, s0 @ encoding: [0x80,0x0a,0x30,0xee]
Some instructions end with an "ls" prefix, but it doesn't indicate that they are conditional. Check for those instructions explicitly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117747 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 23:50:21 +00:00
vadd.f32 s0, s1, s0
Use ARM-style comments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117955 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 21:16:39 +00:00
@ CHECK: vsub.f64 d16, d17, d16 @ encoding: [0xe0,0x0b,0x71,0xee]
Some instructions end with an "ls" prefix, but it doesn't indicate that they are conditional. Check for those instructions explicitly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117747 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 23:50:21 +00:00
vsub.f64 d16, d17, d16
Use ARM-style comments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117955 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 21:16:39 +00:00
@ CHECK: vsub.f32 s0, s1, s0 @ encoding: [0xc0,0x0a,0x30,0xee]
Some instructions end with an "ls" prefix, but it doesn't indicate that they are conditional. Check for those instructions explicitly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117747 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 23:50:21 +00:00
vsub.f32 s0, s1, s0
Use ARM-style comments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117955 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 21:16:39 +00:00
@ CHECK: vdiv.f64 d16, d17, d16 @ encoding: [0xa0,0x0b,0xc1,0xee]
Some instructions end with an "ls" prefix, but it doesn't indicate that they are conditional. Check for those instructions explicitly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117747 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 23:50:21 +00:00
vdiv.f64 d16, d17, d16
Use ARM-style comments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117955 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 21:16:39 +00:00
@ CHECK: vdiv.f32 s0, s1, s0 @ encoding: [0x80,0x0a,0x80,0xee]
Some instructions end with an "ls" prefix, but it doesn't indicate that they are conditional. Check for those instructions explicitly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117747 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 23:50:21 +00:00
vdiv.f32 s0, s1, s0
Use ARM-style comments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117955 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 21:16:39 +00:00
@ CHECK: vmul.f64 d16, d17, d16 @ encoding: [0xa0,0x0b,0x61,0xee]
Some instructions end with an "ls" prefix, but it doesn't indicate that they are conditional. Check for those instructions explicitly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117747 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 23:50:21 +00:00
vmul.f64 d16, d17, d16
ARM assembly parsing for two-operand form of 'mul' instruction. rdar://10449856. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144689 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15 20:14:51 +00:00
@ CHECK: vmul.f64 d20, d20, d17 @ encoding: [0xa1,0x4b,0x64,0xee]
vmul.f64 d20, d17
Use ARM-style comments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117955 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 21:16:39 +00:00
@ CHECK: vmul.f32 s0, s1, s0 @ encoding: [0x80,0x0a,0x20,0xee]
Some instructions end with an "ls" prefix, but it doesn't indicate that they are conditional. Check for those instructions explicitly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117747 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 23:50:21 +00:00
vmul.f32 s0, s1, s0
ARM assembly parsing for two-operand form of 'mul' instruction. rdar://10449856. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144689 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15 20:14:51 +00:00
@ CHECK: vmul.f32 s11, s11, s21 @ encoding: [0xaa,0x5a,0x65,0xee]
vmul.f32 s11, s21
Use ARM-style comments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117955 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 21:16:39 +00:00
@ CHECK: vnmul.f64 d16, d17, d16 @ encoding: [0xe0,0x0b,0x61,0xee]
Some instructions end with an "ls" prefix, but it doesn't indicate that they are conditional. Check for those instructions explicitly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117747 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 23:50:21 +00:00
vnmul.f64 d16, d17, d16
Use ARM-style comments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117955 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 21:16:39 +00:00
@ CHECK: vnmul.f32 s0, s1, s0 @ encoding: [0xc0,0x0a,0x20,0xee]
Some instructions end with an "ls" prefix, but it doesn't indicate that they are conditional. Check for those instructions explicitly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117747 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 23:50:21 +00:00
vnmul.f32 s0, s1, s0
Use ARM-style comments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117955 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 21:16:39 +00:00
@ CHECK: vcmpe.f64 d17, d16 @ encoding: [0xe0,0x1b,0xf4,0xee]
Some instructions end with an "ls" prefix, but it doesn't indicate that they are conditional. Check for those instructions explicitly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117747 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 23:50:21 +00:00
vcmpe.f64 d17, d16
Use ARM-style comments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117955 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 21:16:39 +00:00
@ CHECK: vcmpe.f32 s1, s0 @ encoding: [0xc0,0x0a,0xf4,0xee]
Some instructions end with an "ls" prefix, but it doesn't indicate that they are conditional. Check for those instructions explicitly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117747 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 23:50:21 +00:00
vcmpe.f32 s1, s0
ARM parsing/encoding for VCMP/VCMPE. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141038 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-03 22:30:24 +00:00
@ CHECK: vcmpe.f64 d16, #0 @ encoding: [0xc0,0x0b,0xf5,0xee]
vcmpe.f64 d16, #0
Some instructions end with an "ls" prefix, but it doesn't indicate that they are conditional. Check for those instructions explicitly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117747 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 23:50:21 +00:00
ARM parsing/encoding for VCMP/VCMPE. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141038 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-03 22:30:24 +00:00
@ CHECK: vcmpe.f32 s0, #0 @ encoding: [0xc0,0x0a,0xb5,0xee]
vcmpe.f32 s0, #0
Some instructions end with an "ls" prefix, but it doesn't indicate that they are conditional. Check for those instructions explicitly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117747 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 23:50:21 +00:00
Use ARM-style comments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117955 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 21:16:39 +00:00
@ CHECK: vabs.f64 d16, d16 @ encoding: [0xe0,0x0b,0xf0,0xee]
Some instructions end with an "ls" prefix, but it doesn't indicate that they are conditional. Check for those instructions explicitly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117747 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 23:50:21 +00:00
vabs.f64 d16, d16
Use ARM-style comments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117955 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 21:16:39 +00:00
@ CHECK: vabs.f32 s0, s0 @ encoding: [0xc0,0x0a,0xb0,0xee]
Some instructions end with an "ls" prefix, but it doesn't indicate that they are conditional. Check for those instructions explicitly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117747 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 23:50:21 +00:00
vabs.f32 s0, s0
Improve handling of #-0 offsets for many more pre-indexed addressing modes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138754 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-29 19:36:44 +00:00
Use ARM-style comments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117955 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 21:16:39 +00:00
@ CHECK: vcvt.f32.f64 s0, d16 @ encoding: [0xe0,0x0b,0xb7,0xee]
Some instructions end with an "ls" prefix, but it doesn't indicate that they are conditional. Check for those instructions explicitly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117747 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 23:50:21 +00:00
vcvt.f32.f64 s0, d16
Use ARM-style comments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117955 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 21:16:39 +00:00
@ CHECK: vcvt.f64.f32 d16, s0 @ encoding: [0xc0,0x0a,0xf7,0xee]
Some instructions end with an "ls" prefix, but it doesn't indicate that they are conditional. Check for those instructions explicitly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117747 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 23:50:21 +00:00
vcvt.f64.f32 d16, s0
Use ARM-style comments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117955 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 21:16:39 +00:00
@ CHECK: vneg.f64 d16, d16 @ encoding: [0x60,0x0b,0xf1,0xee]
Some instructions end with an "ls" prefix, but it doesn't indicate that they are conditional. Check for those instructions explicitly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117747 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 23:50:21 +00:00
vneg.f64 d16, d16
Use ARM-style comments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117955 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 21:16:39 +00:00
@ CHECK: vneg.f32 s0, s0 @ encoding: [0x40,0x0a,0xb1,0xee]
Some instructions end with an "ls" prefix, but it doesn't indicate that they are conditional. Check for those instructions explicitly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117747 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 23:50:21 +00:00
vneg.f32 s0, s0
Use ARM-style comments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117955 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 21:16:39 +00:00
@ CHECK: vsqrt.f64 d16, d16 @ encoding: [0xe0,0x0b,0xf1,0xee]
Some instructions end with an "ls" prefix, but it doesn't indicate that they are conditional. Check for those instructions explicitly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117747 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 23:50:21 +00:00
vsqrt.f64 d16, d16
Use ARM-style comments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117955 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 21:16:39 +00:00
@ CHECK: vsqrt.f32 s0, s0 @ encoding: [0xc0,0x0a,0xb1,0xee]
Some instructions end with an "ls" prefix, but it doesn't indicate that they are conditional. Check for those instructions explicitly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117747 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 23:50:21 +00:00
vsqrt.f32 s0, s0
Use ARM-style comments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117955 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 21:16:39 +00:00
@ CHECK: vcvt.f64.s32 d16, s0 @ encoding: [0xc0,0x0b,0xf8,0xee]
Some instructions end with an "ls" prefix, but it doesn't indicate that they are conditional. Check for those instructions explicitly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117747 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 23:50:21 +00:00
vcvt.f64.s32 d16, s0
Use ARM-style comments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117955 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 21:16:39 +00:00
@ CHECK: vcvt.f32.s32 s0, s0 @ encoding: [0xc0,0x0a,0xb8,0xee]
Some instructions end with an "ls" prefix, but it doesn't indicate that they are conditional. Check for those instructions explicitly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117747 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 23:50:21 +00:00
vcvt.f32.s32 s0, s0
Use ARM-style comments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117955 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 21:16:39 +00:00
@ CHECK: vcvt.f64.u32 d16, s0 @ encoding: [0x40,0x0b,0xf8,0xee]
Some instructions end with an "ls" prefix, but it doesn't indicate that they are conditional. Check for those instructions explicitly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117747 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 23:50:21 +00:00
vcvt.f64.u32 d16, s0
Use ARM-style comments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117955 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 21:16:39 +00:00
@ CHECK: vcvt.f32.u32 s0, s0 @ encoding: [0x40,0x0a,0xb8,0xee]
Some instructions end with an "ls" prefix, but it doesn't indicate that they are conditional. Check for those instructions explicitly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117747 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 23:50:21 +00:00
vcvt.f32.u32 s0, s0
Use ARM-style comments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117955 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 21:16:39 +00:00
@ CHECK: vcvt.s32.f64 s0, d16 @ encoding: [0xe0,0x0b,0xbd,0xee]
Some instructions end with an "ls" prefix, but it doesn't indicate that they are conditional. Check for those instructions explicitly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117747 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 23:50:21 +00:00
vcvt.s32.f64 s0, d16
Use ARM-style comments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117955 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 21:16:39 +00:00
@ CHECK: vcvt.s32.f32 s0, s0 @ encoding: [0xc0,0x0a,0xbd,0xee]
Some instructions end with an "ls" prefix, but it doesn't indicate that they are conditional. Check for those instructions explicitly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117747 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 23:50:21 +00:00
vcvt.s32.f32 s0, s0
Use ARM-style comments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117955 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 21:16:39 +00:00
@ CHECK: vcvt.u32.f64 s0, d16 @ encoding: [0xe0,0x0b,0xbc,0xee]
Some instructions end with an "ls" prefix, but it doesn't indicate that they are conditional. Check for those instructions explicitly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117747 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 23:50:21 +00:00
vcvt.u32.f64 s0, d16
Use ARM-style comments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117955 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 21:16:39 +00:00
@ CHECK: vcvt.u32.f32 s0, s0 @ encoding: [0xc0,0x0a,0xbc,0xee]
Some instructions end with an "ls" prefix, but it doesn't indicate that they are conditional. Check for those instructions explicitly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117747 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 23:50:21 +00:00
vcvt.u32.f32 s0, s0
Use ARM-style comments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117955 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 21:16:39 +00:00
@ CHECK: vmla.f64 d16, d18, d17 @ encoding: [0xa1,0x0b,0x42,0xee]
Some instructions end with an "ls" prefix, but it doesn't indicate that they are conditional. Check for those instructions explicitly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117747 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 23:50:21 +00:00
vmla.f64 d16, d18, d17
Use ARM-style comments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117955 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 21:16:39 +00:00
@ CHECK: vmla.f32 s1, s2, s0 @ encoding: [0x00,0x0a,0x41,0xee]
Some instructions end with an "ls" prefix, but it doesn't indicate that they are conditional. Check for those instructions explicitly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117747 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 23:50:21 +00:00
vmla.f32 s1, s2, s0
Use ARM-style comments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117955 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 21:16:39 +00:00
@ CHECK: vmls.f64 d16, d18, d17 @ encoding: [0xe1,0x0b,0x42,0xee]
Some instructions end with an "ls" prefix, but it doesn't indicate that they are conditional. Check for those instructions explicitly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117747 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 23:50:21 +00:00
vmls.f64 d16, d18, d17
Use ARM-style comments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117955 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 21:16:39 +00:00
@ CHECK: vmls.f32 s1, s2, s0 @ encoding: [0x40,0x0a,0x41,0xee]
Some instructions end with an "ls" prefix, but it doesn't indicate that they are conditional. Check for those instructions explicitly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117747 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 23:50:21 +00:00
vmls.f32 s1, s2, s0
Use ARM-style comments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117955 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 21:16:39 +00:00
@ CHECK: vnmla.f64 d16, d18, d17 @ encoding: [0xe1,0x0b,0x52,0xee]
Some instructions end with an "ls" prefix, but it doesn't indicate that they are conditional. Check for those instructions explicitly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117747 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 23:50:21 +00:00
vnmla.f64 d16, d18, d17
Use ARM-style comments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117955 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 21:16:39 +00:00
@ CHECK: vnmla.f32 s1, s2, s0 @ encoding: [0x40,0x0a,0x51,0xee]
Some instructions end with an "ls" prefix, but it doesn't indicate that they are conditional. Check for those instructions explicitly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117747 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 23:50:21 +00:00
vnmla.f32 s1, s2, s0
Use ARM-style comments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117955 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 21:16:39 +00:00
@ CHECK: vnmls.f64 d16, d18, d17 @ encoding: [0xa1,0x0b,0x52,0xee]
Some instructions end with an "ls" prefix, but it doesn't indicate that they are conditional. Check for those instructions explicitly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117747 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 23:50:21 +00:00
vnmls.f64 d16, d18, d17
Use ARM-style comments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117955 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 21:16:39 +00:00
@ CHECK: vnmls.f32 s1, s2, s0 @ encoding: [0x00,0x0a,0x51,0xee]
Some instructions end with an "ls" prefix, but it doesn't indicate that they are conditional. Check for those instructions explicitly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117747 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 23:50:21 +00:00
vnmls.f32 s1, s2, s0
ARM assembly parsing and encoding for VMRS/FMSTAT. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141025 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-03 21:12:43 +00:00
@ CHECK: vmrs apsr_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee]
@ CHECK: vmrs apsr_nzcv, fpscr @ encoding: [0x10,0xfa,0xf1,0xee]
vmrs apsr_nzcv, fpscr
fmstat
Improve handling of #-0 offsets for many more pre-indexed addressing modes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138754 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-29 19:36:44 +00:00
Use ARM-style comments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117955 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 21:16:39 +00:00
@ CHECK: vnegne.f64 d16, d16 @ encoding: [0x60,0x0b,0xf1,0x1e]
Some instructions end with an "ls" prefix, but it doesn't indicate that they are conditional. Check for those instructions explicitly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117747 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 23:50:21 +00:00
vnegne.f64 d16, d16
Use ARM-style comments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117955 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 21:16:39 +00:00
@ CHECK: vmovne s0, r0 @ encoding: [0x10,0x0a,0x00,0x1e]
@ CHECK: vmoveq s0, r1 @ encoding: [0x10,0x1a,0x00,0x0e]
Some instructions end with an "ls" prefix, but it doesn't indicate that they are conditional. Check for those instructions explicitly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117747 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 23:50:21 +00:00
vmovne s0, r0
vmoveq s0, r1
ARM assembly parsing for optional datatype suffix on VFP VMOV GPR<->VFP insns. Yet more of rdar://10435076. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144691 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-15 20:29:42 +00:00
vmov.f32 r1, s2
vmov.f32 s4, r3
vmov.f64 r1, r5, d2
vmov.f64 d4, r3, r9
@ CHECK: vmov r1, s2 @ encoding: [0x10,0x1a,0x11,0xee]
@ CHECK: vmov s4, r3 @ encoding: [0x10,0x3a,0x02,0xee]
@ CHECK: vmov r1, r5, d2 @ encoding: [0x12,0x1b,0x55,0xec]
@ CHECK: vmov d4, r3, r9 @ encoding: [0x14,0x3b,0x49,0xec]
Use ARM-style comments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117955 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 21:16:39 +00:00
@ CHECK: vmrs r0, fpscr @ encoding: [0x10,0x0a,0xf1,0xee]
Some instructions end with an "ls" prefix, but it doesn't indicate that they are conditional. Check for those instructions explicitly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117747 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 23:50:21 +00:00
vmrs r0, fpscr
Create two new generic classes to represent the following VMRS/VMSR variations: vmrs reg, fpexc vmrs reg, fpsid vmsr fpexc, reg vmsr fpsid, reg git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123783 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-18 21:58:20 +00:00
@ CHECK: vmrs r0, fpexc @ encoding: [0x10,0x0a,0xf8,0xee]
vmrs r0, fpexc
@ CHECK: vmrs r0, fpsid @ encoding: [0x10,0x0a,0xf0,0xee]
vmrs r0, fpsid
Some instructions end with an "ls" prefix, but it doesn't indicate that they are conditional. Check for those instructions explicitly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117747 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 23:50:21 +00:00
Use ARM-style comments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117955 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 21:16:39 +00:00
@ CHECK: vmsr fpscr, r0 @ encoding: [0x10,0x0a,0xe1,0xee]
Some instructions end with an "ls" prefix, but it doesn't indicate that they are conditional. Check for those instructions explicitly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117747 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 23:50:21 +00:00
vmsr fpscr, r0
Create two new generic classes to represent the following VMRS/VMSR variations: vmrs reg, fpexc vmrs reg, fpsid vmsr fpexc, reg vmsr fpsid, reg git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123783 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-18 21:58:20 +00:00
@ CHECK: vmsr fpexc, r0 @ encoding: [0x10,0x0a,0xe8,0xee]
vmsr fpexc, r0
@ CHECK: vmsr fpsid, r0 @ encoding: [0x10,0x0a,0xe0,0xee]
vmsr fpsid, r0
Some instructions end with an "ls" prefix, but it doesn't indicate that they are conditional. Check for those instructions explicitly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117747 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 23:50:21 +00:00
ARM assembly parsing and encoding for VMOV immediate. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141046 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-03 23:38:36 +00:00
vmov.f64 d16, #3.000000e+00
vmov.f32 s0, #3.000000e+00
vmov.f64 d16, #-3.000000e+00
vmov.f32 s0, #-3.000000e+00
@ CHECK: vmov.f64 d16, #3.000000e+00 @ encoding: [0x08,0x0b,0xf0,0xee]
@ CHECK: vmov.f32 s0, #3.000000e+00 @ encoding: [0x08,0x0a,0xb0,0xee]
@ CHECK: vmov.f64 d16, #-3.000000e+00 @ encoding: [0x08,0x0b,0xf8,0xee]
@ CHECK: vmov.f32 s0, #-3.000000e+00 @ encoding: [0x08,0x0a,0xb8,0xee]
Some instructions end with an "ls" prefix, but it doesn't indicate that they are conditional. Check for those instructions explicitly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117747 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 23:50:21 +00:00
Use ARM-style comments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117955 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 21:16:39 +00:00
@ CHECK: vmov s0, r0 @ encoding: [0x10,0x0a,0x00,0xee]
@ CHECK: vmov s1, r1 @ encoding: [0x90,0x1a,0x00,0xee]
@ CHECK: vmov s2, r2 @ encoding: [0x10,0x2a,0x01,0xee]
@ CHECK: vmov s3, r3 @ encoding: [0x90,0x3a,0x01,0xee]
Some instructions end with an "ls" prefix, but it doesn't indicate that they are conditional. Check for those instructions explicitly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117747 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 23:50:21 +00:00
vmov s0, r0
vmov s1, r1
vmov s2, r2
vmov s3, r3
Use ARM-style comments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117955 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 21:16:39 +00:00
@ CHECK: vmov r0, s0 @ encoding: [0x10,0x0a,0x10,0xee]
@ CHECK: vmov r1, s1 @ encoding: [0x90,0x1a,0x10,0xee]
@ CHECK: vmov r2, s2 @ encoding: [0x10,0x2a,0x11,0xee]
@ CHECK: vmov r3, s3 @ encoding: [0x90,0x3a,0x11,0xee]
Some instructions end with an "ls" prefix, but it doesn't indicate that they are conditional. Check for those instructions explicitly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117747 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 23:50:21 +00:00
vmov r0, s0
vmov r1, s1
vmov r2, s2
vmov r3, s3
Use ARM-style comments. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117955 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-01 21:16:39 +00:00
@ CHECK: vmov r0, r1, d16 @ encoding: [0x30,0x0b,0x51,0xec]
Some instructions end with an "ls" prefix, but it doesn't indicate that they are conditional. Check for those instructions explicitly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117747 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-29 23:50:21 +00:00
vmov r0, r1, d16
Rename getAddrModeImm12OpValue to getAddrModeImmOpValue and expand it to work with immediates up to 16-bits in size. The same logic is applied to other LDR encodings, e.g. VLDR, but which use a different immediate bit width (8-bits in VLDR's case). Removing the "12" allows it to be more generic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118094 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-02 22:31:46 +00:00
ARM VLDR/VSTR instructions don't need a size suffix. Canonicallize on the non-suffixed form, but continue to accept assembly that has any correctly sized type suffix. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144583 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14 23:03:21 +00:00
@ CHECK: vldr d17, [r0] @ encoding: [0x00,0x1b,0xd0,0xed]
@ CHECK: vldr s0, [lr] @ encoding: [0x00,0x0a,0x9e,0xed]
@ CHECK: vldr d0, [lr] @ encoding: [0x00,0x0b,0x9e,0xed]
ARM optional size suffix for VLDR/VSTR syntax. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144427 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11 23:34:43 +00:00
Rename getAddrModeImm12OpValue to getAddrModeImmOpValue and expand it to work with immediates up to 16-bits in size. The same logic is applied to other LDR encodings, e.g. VLDR, but which use a different immediate bit width (8-bits in VLDR's case). Removing the "12" allows it to be more generic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118094 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-02 22:31:46 +00:00
vldr.64 d17, [r0]
ARM VLDR/VSTR instructions don't need a size suffix. Canonicallize on the non-suffixed form, but continue to accept assembly that has any correctly sized type suffix. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144583 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14 23:03:21 +00:00
vldr.i32 s0, [lr]
vldr.d d0, [lr]
Rename getAddrModeImm12OpValue to getAddrModeImmOpValue and expand it to work with immediates up to 16-bits in size. The same logic is applied to other LDR encodings, e.g. VLDR, but which use a different immediate bit width (8-bits in VLDR's case). Removing the "12" allows it to be more generic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118094 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-02 22:31:46 +00:00
ARM VLDR/VSTR instructions don't need a size suffix. Canonicallize on the non-suffixed form, but continue to accept assembly that has any correctly sized type suffix. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144583 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14 23:03:21 +00:00
@ CHECK: vldr d1, [r2, #32] @ encoding: [0x08,0x1b,0x92,0xed]
@ CHECK: vldr d1, [r2, #-32] @ encoding: [0x08,0x1b,0x12,0xed]
Rename getAddrModeImm12OpValue to getAddrModeImmOpValue and expand it to work with immediates up to 16-bits in size. The same logic is applied to other LDR encodings, e.g. VLDR, but which use a different immediate bit width (8-bits in VLDR's case). Removing the "12" allows it to be more generic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118094 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-02 22:31:46 +00:00
vldr.64 d1, [r2, #32]
ARM VLDR/VSTR instructions don't need a size suffix. Canonicallize on the non-suffixed form, but continue to accept assembly that has any correctly sized type suffix. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144583 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14 23:03:21 +00:00
vldr.f64 d1, [r2, #-32]
Improve handling of #-0 offsets for many more pre-indexed addressing modes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138754 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-29 19:36:44 +00:00
ARM VLDR/VSTR instructions don't need a size suffix. Canonicallize on the non-suffixed form, but continue to accept assembly that has any correctly sized type suffix. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144583 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14 23:03:21 +00:00
@ CHECK: vldr d2, [r3] @ encoding: [0x00,0x2b,0x93,0xed]
Rename getAddrModeImm12OpValue to getAddrModeImmOpValue and expand it to work with immediates up to 16-bits in size. The same logic is applied to other LDR encodings, e.g. VLDR, but which use a different immediate bit width (8-bits in VLDR's case). Removing the "12" allows it to be more generic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118094 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-02 22:31:46 +00:00
vldr.64 d2, [r3]
ARM VLDR/VSTR instructions don't need a size suffix. Canonicallize on the non-suffixed form, but continue to accept assembly that has any correctly sized type suffix. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144583 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14 23:03:21 +00:00
@ CHECK: vldr d3, [pc] @ encoding: [0x00,0x3b,0x9f,0xed]
@ CHECK: vldr d3, [pc] @ encoding: [0x00,0x3b,0x9f,0xed]
@ CHECK: vldr d3, [pc, #-0] @ encoding: [0x00,0x3b,0x1f,0xed]
Rename getAddrModeImm12OpValue to getAddrModeImmOpValue and expand it to work with immediates up to 16-bits in size. The same logic is applied to other LDR encodings, e.g. VLDR, but which use a different immediate bit width (8-bits in VLDR's case). Removing the "12" allows it to be more generic. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118094 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-02 22:31:46 +00:00
vldr.64 d3, [pc]
vldr.64 d3, [pc,#0]
vldr.64 d3, [pc,#-0]
The MC code couldn't handle ARM LDR instructions with negative offsets: vldr.64 d1, [r0, #-32] The problem was with how the addressing mode 5 encodes the offsets. This change makes sure that the way offsets are handled in addressing mode 5 is consistent throughout the MC code. It involves re-refactoring the "getAddrModeImmOpValue" method into an "Imm12" and "addressing mode 5" version. But not to worry! The majority of the duplicated code has been unified. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118144 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-03 01:49:29 +00:00
ARM VLDR/VSTR instructions don't need a size suffix. Canonicallize on the non-suffixed form, but continue to accept assembly that has any correctly sized type suffix. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144583 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14 23:03:21 +00:00
@ CHECK: vldr s13, [r0] @ encoding: [0x00,0x6a,0xd0,0xed]
The MC code couldn't handle ARM LDR instructions with negative offsets: vldr.64 d1, [r0, #-32] The problem was with how the addressing mode 5 encodes the offsets. This change makes sure that the way offsets are handled in addressing mode 5 is consistent throughout the MC code. It involves re-refactoring the "getAddrModeImmOpValue" method into an "Imm12" and "addressing mode 5" version. But not to worry! The majority of the duplicated code has been unified. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118144 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-03 01:49:29 +00:00
vldr.32 s13, [r0]
ARM VLDR/VSTR instructions don't need a size suffix. Canonicallize on the non-suffixed form, but continue to accept assembly that has any correctly sized type suffix. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144583 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14 23:03:21 +00:00
@ CHECK: vldr s1, [r2, #32] @ encoding: [0x08,0x0a,0xd2,0xed]
@ CHECK: vldr s1, [r2, #-32] @ encoding: [0x08,0x0a,0x52,0xed]
The MC code couldn't handle ARM LDR instructions with negative offsets: vldr.64 d1, [r0, #-32] The problem was with how the addressing mode 5 encodes the offsets. This change makes sure that the way offsets are handled in addressing mode 5 is consistent throughout the MC code. It involves re-refactoring the "getAddrModeImmOpValue" method into an "Imm12" and "addressing mode 5" version. But not to worry! The majority of the duplicated code has been unified. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118144 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-03 01:49:29 +00:00
vldr.32 s1, [r2, #32]
vldr.32 s1, [r2, #-32]
Improve handling of #-0 offsets for many more pre-indexed addressing modes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138754 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-29 19:36:44 +00:00
ARM VLDR/VSTR instructions don't need a size suffix. Canonicallize on the non-suffixed form, but continue to accept assembly that has any correctly sized type suffix. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144583 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14 23:03:21 +00:00
@ CHECK: vldr s2, [r3] @ encoding: [0x00,0x1a,0x93,0xed]
The MC code couldn't handle ARM LDR instructions with negative offsets: vldr.64 d1, [r0, #-32] The problem was with how the addressing mode 5 encodes the offsets. This change makes sure that the way offsets are handled in addressing mode 5 is consistent throughout the MC code. It involves re-refactoring the "getAddrModeImmOpValue" method into an "Imm12" and "addressing mode 5" version. But not to worry! The majority of the duplicated code has been unified. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118144 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-03 01:49:29 +00:00
vldr.32 s2, [r3]
ARM VLDR/VSTR instructions don't need a size suffix. Canonicallize on the non-suffixed form, but continue to accept assembly that has any correctly sized type suffix. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144583 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14 23:03:21 +00:00
@ CHECK: vldr s5, [pc] @ encoding: [0x00,0x2a,0xdf,0xed]
@ CHECK: vldr s5, [pc] @ encoding: [0x00,0x2a,0xdf,0xed]
@ CHECK: vldr s5, [pc, #-0] @ encoding: [0x00,0x2a,0x5f,0xed]
The MC code couldn't handle ARM LDR instructions with negative offsets: vldr.64 d1, [r0, #-32] The problem was with how the addressing mode 5 encodes the offsets. This change makes sure that the way offsets are handled in addressing mode 5 is consistent throughout the MC code. It involves re-refactoring the "getAddrModeImmOpValue" method into an "Imm12" and "addressing mode 5" version. But not to worry! The majority of the duplicated code has been unified. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118144 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-03 01:49:29 +00:00
vldr.32 s5, [pc]
vldr.32 s5, [pc,#0]
vldr.32 s5, [pc,#-0]
Add encoding for VSTR. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118220 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-04 00:59:42 +00:00
ARM VLDR/VSTR instructions don't need a size suffix. Canonicallize on the non-suffixed form, but continue to accept assembly that has any correctly sized type suffix. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144583 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14 23:03:21 +00:00
@ CHECK: vstr d4, [r1] @ encoding: [0x00,0x4b,0x81,0xed]
@ CHECK: vstr d4, [r1, #24] @ encoding: [0x06,0x4b,0x81,0xed]
@ CHECK: vstr d4, [r1, #-24] @ encoding: [0x06,0x4b,0x01,0xed]
@ CHECK: vstr s0, [lr] @ encoding: [0x00,0x0a,0x8e,0xed]
@ CHECK: vstr d0, [lr] @ encoding: [0x00,0x0b,0x8e,0xed]
ARM optional size suffix for VLDR/VSTR syntax. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144427 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11 23:34:43 +00:00
Add encoding for VSTR. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118220 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-04 00:59:42 +00:00
vstr.64 d4, [r1]
vstr.64 d4, [r1, #24]
vstr.64 d4, [r1, #-24]
ARM optional size suffix for VLDR/VSTR syntax. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144427 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11 23:34:43 +00:00
vstr s0, [lr]
vstr d0, [lr]
Add encoding for VSTR. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118220 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-04 00:59:42 +00:00
ARM VLDR/VSTR instructions don't need a size suffix. Canonicallize on the non-suffixed form, but continue to accept assembly that has any correctly sized type suffix. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144583 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14 23:03:21 +00:00
@ CHECK: vstr s4, [r1] @ encoding: [0x00,0x2a,0x81,0xed]
@ CHECK: vstr s4, [r1, #24] @ encoding: [0x06,0x2a,0x81,0xed]
@ CHECK: vstr s4, [r1, #-24] @ encoding: [0x06,0x2a,0x01,0xed]
Add encoding for VSTR. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118220 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-04 00:59:42 +00:00
vstr.32 s4, [r1]
vstr.32 s4, [r1, #24]
vstr.32 s4, [r1, #-24]
Proper encoding for VLDM and VSTM instructions. The register lists for these instructions have to distinguish between lists of single- and double-precision registers in order for the ASM matcher to do a proper job. In all other respects, a list of single- or double-precision registers are the same as a list of GPR registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119460 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-17 04:32:08 +00:00
@ CHECK: vldmia r1, {d2, d3, d4, d5, d6, d7} @ encoding: [0x0c,0x2b,0x91,0xec]
@ CHECK: vldmia r1, {s2, s3, s4, s5, s6, s7} @ encoding: [0x06,0x1a,0x91,0xec]
vldmia r1, {d2,d3-d6,d7}
vldmia r1, {s2,s3-s6,s7}
@ CHECK: vstmia r1, {d2, d3, d4, d5, d6, d7} @ encoding: [0x0c,0x2b,0x81,0xec]
@ CHECK: vstmia r1, {s2, s3, s4, s5, s6, s7} @ encoding: [0x06,0x1a,0x81,0xec]
ARM allow Q registers in vldm/vstm register lists. rdar://9672822 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144407 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11 21:27:40 +00:00
@ CHECK: vpush {d8, d9, d10, d11, d12, d13, d14, d15} @ encoding: [0x10,0x8b,0x2d,0xed]
Proper encoding for VLDM and VSTM instructions. The register lists for these instructions have to distinguish between lists of single- and double-precision registers in order for the ASM matcher to do a proper job. In all other respects, a list of single- or double-precision registers are the same as a list of GPR registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119460 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-17 04:32:08 +00:00
vstmia r1, {d2,d3-d6,d7}
vstmia r1, {s2,s3-s6,s7}
ARM allow Q registers in vldm/vstm register lists. rdar://9672822 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144407 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-11 21:27:40 +00:00
vstmdb sp!, {q4-q7}
Add encoding testcases for ARM vcvtr variations git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124289 91177308-0d34-0410-b5e6-96231b3b80d8
2011-01-26 13:53:38 +00:00
@ CHECK: vcvtr.s32.f64 s0, d0 @ encoding: [0x40,0x0b,0xbd,0xee]
@ CHECK: vcvtr.s32.f32 s0, s1 @ encoding: [0x60,0x0a,0xbd,0xee]
@ CHECK: vcvtr.u32.f64 s0, d0 @ encoding: [0x40,0x0b,0xbc,0xee]
@ CHECK: vcvtr.u32.f32 s0, s1 @ encoding: [0x60,0x0a,0xbc,0xee]
vcvtr.s32.f64 s0, d0
vcvtr.s32.f32 s0, s1
vcvtr.u32.f64 s0, d0
vcvtr.u32.f32 s0, s1
Add missing encoding information for some of the GPR<->FP register moves. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138780 91177308-0d34-0410-b5e6-96231b3b80d8
2011-08-29 23:15:25 +00:00
@ CHECK: vmovne s25, s26, r2, r5
vmovne s25, s26, r2, r5 @ encoding: [0x39,0x2a,0x45,0x1c]
ARM VFP optional data type on VMOV GPR<-->SPR. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147104 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-21 23:24:15 +00:00
@ VMOV w/ optional data type suffix.
vmov.32 s1, r8
vmov.s16 s2, r4
vmov.16 s3, r6
vmov.u32 s4, r1
vmov.p8 s5, r2
vmov.8 s6, r3
vmov.32 r1, s8
vmov.s16 r2, s4
vmov.16 r3, s6
vmov.u32 r4, s1
vmov.p8 r5, s2
vmov.8 r6, s3
@ CHECK: vmov s1, r8 @ encoding: [0x90,0x8a,0x00,0xee]
@ CHECK: vmov s2, r4 @ encoding: [0x10,0x4a,0x01,0xee]
@ CHECK: vmov s3, r6 @ encoding: [0x90,0x6a,0x01,0xee]
@ CHECK: vmov s4, r1 @ encoding: [0x10,0x1a,0x02,0xee]
@ CHECK: vmov s5, r2 @ encoding: [0x90,0x2a,0x02,0xee]
@ CHECK: vmov s6, r3 @ encoding: [0x10,0x3a,0x03,0xee]
@ CHECK: vmov r1, s8 @ encoding: [0x10,0x1a,0x14,0xee]
@ CHECK: vmov r2, s4 @ encoding: [0x10,0x2a,0x12,0xee]
@ CHECK: vmov r3, s6 @ encoding: [0x10,0x3a,0x13,0xee]
@ CHECK: vmov r4, s1 @ encoding: [0x90,0x4a,0x10,0xee]
@ CHECK: vmov r5, s2 @ encoding: [0x10,0x5a,0x11,0xee]
@ CHECK: vmov r6, s3 @ encoding: [0x90,0x6a,0x11,0xee]
ARM VFP assembly parsing and encoding for VCVT(float <--> fixed point). rdar://10558523 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147189 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-22 22:19:05 +00:00
@ VCVT (between floating-point and fixed-point)
vcvt.f32.u32 s0, s0, #20
vcvt.f64.s32 d0, d0, #32
vcvt.f32.u16 s0, s0, #1
vcvt.f64.s16 d0, d0, #16
@ CHECK: vcvt.f32.u32 s0, s0, #20 @ encoding: [0xc6,0x0a,0xbb,0xee]
@ CHECK: vcvt.f64.s32 d0, d0, #32 @ encoding: [0xc0,0x0b,0xba,0xee]
@ CHECK: vcvt.f32.u16 s0, s0, #1 @ encoding: [0x67,0x0a,0xbb,0xee]
@ CHECK: vcvt.f64.s16 d0, d0, #16 @ encoding: [0x40,0x0b,0xba,0xee]
NEON use vmov.i32 to splat some f32 values into vectors. For bit patterns that aren't representable using the 8-bit floating point representation for vmov.f32, but are representable via vmov.i32, treat the .f32 syntax as an alias. Most importantly, this covers the case 'vmov.f32 Vd, #0.0'. rdar://10616677 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148556 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-20 18:09:51 +00:00
@ Use NEON to load some f32 immediates that don't fit the f8 representation.
vmov.f32 d4, #0.0
vmov.f32 d4, #32.0
@ CHECK: vmov.i32 d4, #0x0 @ encoding: [0x10,0x40,0x80,0xf2]
@ CHECK: vmov.i32 d4, #0x42000000 @ encoding: [0x12,0x46,0x84,0xf2]
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