llvm-6502/test/MC/Disassembler/ARM/basic-arm-instructions-v8.txt

# RUN: llvm-mc -disassemble -triple armv8 -show-encoding < %s | FileCheck %s

# New v8 ARM instructions

# HLT

0x70 0x00 0x00 0xe1
# CHECK: hlt #0

0x7f 0xff 0x0f 0xe1
# CHECK: hlt #65535
Add AArch32 DCPS{1,2,3} and HLT instructions. These were pretty straightforward instructions, with some assembly support required for HLT. The ARM assembler is keen to split the instruction mnemonic into a (non-existent) 'H' instruction with the LT condition code. An exception for HLT is needed. HLT follows the same rules as BKPT when in IT blocks, so the special BKPT hadling code has been adapted to handle HLT also. Regression tests added including diagnostic tests for out of range immediates and illegal condition codes, as well as negative tests for pre-ARMv8. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190053 91177308-0d34-0410-b5e6-96231b3b80d8 2013-09-05 14:14:19 +00:00			`# RUN: llvm-mc -disassemble -triple armv8 -show-encoding < %s \| FileCheck %s`

			`# New v8 ARM instructions`

			`# HLT`

			`0x70 0x00 0x00 0xe1`
			`# CHECK: hlt #0`

			`0x7f 0xff 0x0f 0xe1`
			`# CHECK: hlt #65535`