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llvm-6502/test/MC/Disassembler/ARM/invalid-MRRC2-arm.txt

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Added support for unpredictable mcrr/mcrr2/mrrc/mrrc2 ARM instruction in the disassembler. Since the upredicability conditions are complex, C++ code was added to handle them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155001 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-18 13:12:50 +00:00
# RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi |& FileCheck %s
# CHECK: invalid instruction encoding
0x00 0x1a 0x50 0xfc
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