llvm-6502/test/MC/Hexagon/inst_select.ll

;; RUN: llc -mtriple=hexagon-unknown-elf -filetype=obj %s -o - \
;; RUN: | llvm-objdump -s - | FileCheck %s

define i32 @foo (i1 %a, i32 %b, i32 %c)
{
  %1 = select i1 %a, i32 %b, i32 %c
  ret i32 %1
}

; CHECK:  0000 00400085 004201f4 00c09f52
[Hexagon] Adding C2_mux instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222784 91177308-0d34-0410-b5e6-96231b3b80d8 2014-11-25 20:20:09 +00:00			`;; RUN: llc -mtriple=hexagon-unknown-elf -filetype=obj %s -o - \`
			`;; RUN: \| llvm-objdump -s - \| FileCheck %s`

			`define i32 @foo (i1 %a, i32 %b, i32 %c)`
			`{`
			`%1 = select i1 %a, i32 %b, i32 %c`
			`ret i32 %1`
			`}`

[Hexagon] Updating predicate register transfers and adding tstbit to allow select selection. Updating ll tests with predicate transfers that previously had nop encodings. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223800 91177308-0d34-0410-b5e6-96231b3b80d8 2014-12-09 18:16:49 +00:00			`; CHECK: 0000 00400085 004201f4 00c09f52`