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llvm-6502/test/MC/ARM/neon-vst-encoding.s

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Add correct encodings for the basic form of vst1. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118067 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-02 21:06:06 +00:00
@ RUN: llvm-mc -mcpu=cortex-a8 -triple armv7-apple-darwin -show-encoding < %s | FileCheck %s
ARM VLD1/VST1 (one register, no writeback) assembly parsing and encoding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142583 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-20 15:04:25 +00:00
vst1.8 {d16}, [r0, :64]
Enable some VST1 tests and add a few more. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145443 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-29 22:40:32 +00:00
vst1.16 {d16}, [r0]
vst1.32 {d16}, [r0]
vst1.64 {d16}, [r0]
vst1.8 {d16, d17}, [r0, :64]
vst1.16 {d16, d17}, [r0, :128]
vst1.32 {d16, d17}, [r0]
vst1.64 {d16, d17}, [r0]
vst1.8 {d16, d17, d18}, [r0, :64]
vst1.8 {d16, d17, d18}, [r0, :64]!
vst1.8 {d16, d17, d18}, [r0], r3
ARM assembly parsing and encoding for four-register VST1. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145450 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-29 22:58:48 +00:00
vst1.8 {d16, d17, d18, d19}, [r0, :64]
vst1.16 {d16, d17, d18, d19}, [r1, :64]!
vst1.64 {d16, d17, d18, d19}, [r3], r2
Add correct encodings for the basic form of vst1. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118067 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-02 21:06:06 +00:00
Tidy up formatting. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142582 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-20 14:57:47 +00:00
@ CHECK: vst1.8 {d16}, [r0, :64] @ encoding: [0x1f,0x07,0x40,0xf4]
Enable some VST1 tests and add a few more. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145443 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-29 22:40:32 +00:00
@ CHECK: vst1.16 {d16}, [r0] @ encoding: [0x4f,0x07,0x40,0xf4]
@ CHECK: vst1.32 {d16}, [r0] @ encoding: [0x8f,0x07,0x40,0xf4]
@ CHECK: vst1.64 {d16}, [r0] @ encoding: [0xcf,0x07,0x40,0xf4]
@ CHECK: vst1.8 {d16, d17}, [r0, :64] @ encoding: [0x1f,0x0a,0x40,0xf4]
@ CHECK: vst1.16 {d16, d17}, [r0, :128] @ encoding: [0x6f,0x0a,0x40,0xf4]
@ CHECK: vst1.32 {d16, d17}, [r0] @ encoding: [0x8f,0x0a,0x40,0xf4]
@ CHECK: vst1.64 {d16, d17}, [r0] @ encoding: [0xcf,0x0a,0x40,0xf4]
@ CHECK: vst1.8 {d16, d17, d18}, [r0, :64] @ encoding: [0x1f,0x06,0x40,0xf4]
@ CHECK: vst1.8 {d16, d17, d18}, [r0, :64]! @ encoding: [0x1d,0x06,0x40,0xf4]
@ CHECK: vst1.8 {d16, d17, d18}, [r0], r3 @ encoding: [0x03,0x06,0x40,0xf4]
ARM assembly parsing and encoding for four-register VST1. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145450 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-29 22:58:48 +00:00
@ CHECK: vst1.8 {d16, d17, d18, d19}, [r0, :64] @ encoding: [0x1f,0x02,0x40,0xf4]
@ CHECK: vst1.16 {d16, d17, d18, d19}, [r1, :64]! @ encoding: [0x5d,0x02,0x41,0xf4]
@ CHECK: vst1.64 {d16, d17, d18, d19}, [r3], r2 @ encoding: [0xc2,0x02,0x43,0xf4]
ARM VLD1/VST1 (one register, no writeback) assembly parsing and encoding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142583 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-20 15:04:25 +00:00
ARM NEON VST2 assembly parsing and encoding. Work in progress. Parsing for non-writeback, single spaced register lists works now. The rest have the representations better factored, but still need more to be able to parse properly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146579 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14 19:35:22 +00:00
vst2.8 {d16, d17}, [r0, :64]
vst2.16 {d16, d17}, [r0, :128]
vst2.32 {d16, d17}, [r0]
vst2.8 {d16, d17, d18, d19}, [r0, :64]
vst2.16 {d16, d17, d18, d19}, [r0, :128]
vst2.32 {d16, d17, d18, d19}, [r0, :256]
ARM NEON fix alignment encoding for VST2 w/ writeback. Add tests for w/ writeback instruction parsing and encoding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146594 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14 21:49:24 +00:00
vst2.8 {d16, d17}, [r0, :64]!
vst2.16 {q15}, [r0, :128]!
vst2.32 {d14, d15}, [r0]!
vst2.8 {d16, d17, d18, d19}, [r0, :64]!
vst2.16 {d18-d21}, [r0, :128]!
vst2.32 {q4, q5}, [r0, :256]!
ARM NEON VST2 assembly parsing and encoding. Work in progress. Parsing for non-writeback, single spaced register lists works now. The rest have the representations better factored, but still need more to be able to parse properly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146579 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14 19:35:22 +00:00
@ CHECK: vst2.8 {d16, d17}, [r0, :64] @ encoding: [0x1f,0x08,0x40,0xf4]
@ CHECK: vst2.16 {d16, d17}, [r0, :128] @ encoding: [0x6f,0x08,0x40,0xf4]
@ CHECK: vst2.32 {d16, d17}, [r0] @ encoding: [0x8f,0x08,0x40,0xf4]
@ CHECK: vst2.8 {d16, d17, d18, d19}, [r0, :64] @ encoding: [0x1f,0x03,0x40,0xf4]
@ CHECK: vst2.16 {d16, d17, d18, d19}, [r0, :128] @ encoding: [0x6f,0x03,0x40,0xf4]
@ CHECK: vst2.32 {d16, d17, d18, d19}, [r0, :256] @ encoding: [0xbf,0x03,0x40,0xf4]
ARM NEON fix alignment encoding for VST2 w/ writeback. Add tests for w/ writeback instruction parsing and encoding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146594 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14 21:49:24 +00:00
@ CHECK: vst2.8 {d16, d17}, [r0, :64]! @ encoding: [0x1d,0x08,0x40,0xf4]
@ CHECK: vst2.16 {d30, d31}, [r0, :128]! @ encoding: [0x6d,0xe8,0x40,0xf4]
@ CHECK: vst2.32 {d14, d15}, [r0]! @ encoding: [0x8d,0xe8,0x00,0xf4]
@ CHECK: vst2.8 {d16, d17, d18, d19}, [r0, :64]! @ encoding: [0x1d,0x03,0x40,0xf4]
@ CHECK: vst2.16 {d18, d19, d20, d21}, [r0, :128]! @ encoding: [0x6d,0x23,0x40,0xf4]
@ CHECK: vst2.32 {d8, d9, d10, d11}, [r0, :256]! @ encoding: [0xbd,0x83,0x00,0xf4]
ARM VLD1/VST1 (one register, no writeback) assembly parsing and encoding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142583 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-20 15:04:25 +00:00
NEON VST3(multiple 3-element structures) assembly parsing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148748 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-23 23:45:44 +00:00
vst3.8 {d16, d17, d18}, [r1]
vst3.16 {d6, d7, d8}, [r2]
vst3.32 {d1, d2, d3}, [r3]
vst3.8 {d16, d18, d20}, [r0, :64]
vst3.u16 {d27, d29, d31}, [r4]
vst3.i32 {d6, d8, d10}, [r5]
ARM VLD1/VST1 (one register, no writeback) assembly parsing and encoding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142583 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-20 15:04:25 +00:00
NEON VST3(multiple 3-element structures) assembly parsing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148748 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-23 23:45:44 +00:00
vst3.i8 {d12, d13, d14}, [r6], r1
vst3.i16 {d11, d12, d13}, [r7], r2
vst3.u32 {d2, d3, d4}, [r8], r3
vst3.8 {d4, d6, d8}, [r9], r4
vst3.u16 {d14, d16, d18}, [r9], r4
vst3.i32 {d16, d18, d20}, [r10], r5
vst3.p8 {d6, d7, d8}, [r8]!
vst3.16 {d9, d10, d11}, [r7]!
vst3.f32 {d1, d2, d3}, [r6]!
vst3.8 {d16, d18, d20}, [r0, :64]!
vst3.p16 {d20, d22, d24}, [r5]!
vst3.32 {d5, d7, d9}, [r4]!
@ CHECK: vst3.8 {d16, d17, d18}, [r1] @ encoding: [0x0f,0x04,0x41,0xf4]
@ CHECK: vst3.16 {d6, d7, d8}, [r2] @ encoding: [0x4f,0x64,0x02,0xf4]
@ CHECK: vst3.32 {d1, d2, d3}, [r3] @ encoding: [0x8f,0x14,0x03,0xf4]
@ CHECK: vst3.8 {d16, d18, d20}, [r0, :64] @ encoding: [0x1f,0x05,0x40,0xf4]
@ CHECK: vst3.16 {d27, d29, d31}, [r4] @ encoding: [0x4f,0xb5,0x44,0xf4]
@ CHECK: vst3.32 {d6, d8, d10}, [r5] @ encoding: [0x8f,0x65,0x05,0xf4]
@ CHECK: vst3.8 {d12, d13, d14}, [r6], r1 @ encoding: [0x01,0xc4,0x06,0xf4]
@ CHECK: vst3.16 {d11, d12, d13}, [r7], r2 @ encoding: [0x42,0xb4,0x07,0xf4]
@ CHECK: vst3.32 {d2, d3, d4}, [r8], r3 @ encoding: [0x83,0x24,0x08,0xf4]
@ CHECK: vst3.8 {d4, d6, d8}, [r9], r4 @ encoding: [0x04,0x45,0x09,0xf4]
@ CHECK: vst3.16 {d14, d16, d18}, [r9], r4 @ encoding: [0x44,0xe5,0x09,0xf4]
@ CHECK: vst3.32 {d16, d18, d20}, [r10], r5 @ encoding: [0x85,0x05,0x4a,0xf4]
@ CHECK: vst3.8 {d6, d7, d8}, [r8]! @ encoding: [0x0d,0x64,0x08,0xf4]
@ CHECK: vst3.16 {d9, d10, d11}, [r7]! @ encoding: [0x4d,0x94,0x07,0xf4]
@ CHECK: vst3.32 {d1, d2, d3}, [r6]! @ encoding: [0x8d,0x14,0x06,0xf4]
@ CHECK: vst3.8 {d16, d18, d20}, [r0, :64]! @ encoding: [0x1d,0x05,0x40,0xf4]
@ CHECK: vst3.16 {d20, d22, d24}, [r5]! @ encoding: [0x4d,0x45,0x45,0xf4]
@ CHECK: vst3.32 {d5, d7, d9}, [r4]! @ encoding: [0x8d,0x55,0x04,0xf4]
ARM VLD1/VST1 (one register, no writeback) assembly parsing and encoding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142583 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-20 15:04:25 +00:00
NEON VST4(multiple 4 element structures) assembly parsing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148764 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24 00:58:13 +00:00
vst4.8 {d16, d17, d18, d19}, [r1, :64]
vst4.16 {d16, d17, d18, d19}, [r2, :128]
vst4.32 {d16, d17, d18, d19}, [r3, :256]
vst4.8 {d17, d19, d21, d23}, [r5, :256]
vst4.16 {d17, d19, d21, d23}, [r7]
vst4.32 {d16, d18, d20, d22}, [r8]
vst4.s8 {d16, d17, d18, d19}, [r1, :64]!
vst4.s16 {d16, d17, d18, d19}, [r2, :128]!
vst4.s32 {d16, d17, d18, d19}, [r3, :256]!
vst4.u8 {d17, d19, d21, d23}, [r5, :256]!
vst4.u16 {d17, d19, d21, d23}, [r7]!
vst4.u32 {d16, d18, d20, d22}, [r8]!
vst4.p8 {d16, d17, d18, d19}, [r1, :64], r8
vst4.p16 {d16, d17, d18, d19}, [r2], r7
vst4.f32 {d16, d17, d18, d19}, [r3, :64], r5
vst4.i8 {d16, d18, d20, d22}, [r4, :256], r2
vst4.i16 {d16, d18, d20, d22}, [r6], r3
vst4.i32 {d17, d19, d21, d23}, [r9], r4
@ CHECK: vst4.8 {d16, d17, d18, d19}, [r1, :64] @ encoding: [0x1f,0x00,0x41,0xf4]
@ CHECK: vst4.16 {d16, d17, d18, d19}, [r2, :128] @ encoding: [0x6f,0x00,0x42,0xf4]
@ CHECK: vst4.32 {d16, d17, d18, d19}, [r3, :256] @ encoding: [0xbf,0x00,0x43,0xf4]
@ CHECK: vst4.8 {d17, d19, d21, d23}, [r5, :256] @ encoding: [0x3f,0x11,0x45,0xf4]
@ CHECK: vst4.16 {d17, d19, d21, d23}, [r7] @ encoding: [0x4f,0x11,0x47,0xf4]
@ CHECK: vst4.32 {d16, d18, d20, d22}, [r8] @ encoding: [0x8f,0x01,0x48,0xf4]
@ CHECK: vst4.8 {d16, d17, d18, d19}, [r1, :64]! @ encoding: [0x1d,0x00,0x41,0xf4]
@ CHECK: vst4.16 {d16, d17, d18, d19}, [r2, :128]! @ encoding: [0x6d,0x00,0x42,0xf4]
@ CHECK: vst4.32 {d16, d17, d18, d19}, [r3, :256]! @ encoding: [0xbd,0x00,0x43,0xf4]
@ CHECK: vst4.8 {d17, d19, d21, d23}, [r5, :256]! @ encoding: [0x3d,0x11,0x45,0xf4]
@ CHECK: vst4.16 {d17, d19, d21, d23}, [r7]! @ encoding: [0x4d,0x11,0x47,0xf4]
@ CHECK: vst4.32 {d16, d18, d20, d22}, [r8]! @ encoding: [0x8d,0x01,0x48,0xf4]
@ CHECK: vst4.8 {d16, d17, d18, d19}, [r1, :64], r8 @ encoding: [0x18,0x00,0x41,0xf4]
@ CHECK: vst4.16 {d16, d17, d18, d19}, [r2], r7 @ encoding: [0x47,0x00,0x42,0xf4]
@ CHECK: vst4.32 {d16, d17, d18, d19}, [r3, :64], r5 @ encoding: [0x95,0x00,0x43,0xf4]
@ CHECK: vst4.8 {d16, d18, d20, d22}, [r4, :256], r2 @ encoding: [0x32,0x01,0x44,0xf4]
@ CHECK: vst4.16 {d16, d18, d20, d22}, [r6], r3 @ encoding: [0x43,0x01,0x46,0xf4]
@ CHECK: vst4.32 {d17, d19, d21, d23}, [r9], r4 @ encoding: [0x84,0x11,0x49,0xf4]
ARM VLD1/VST1 (one register, no writeback) assembly parsing and encoding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142583 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-20 15:04:25 +00:00
ARM enable a few more tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146985 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 20:03:00 +00:00
vst2.8 {d16[1], d17[1]}, [r0, :16]
Simplify some NEON assembly pseudo definitions. Let the generic token alias definitions handle the data subtype suffices. We don't need explicit versions for each. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148718 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-23 19:39:08 +00:00
vst2.p16 {d16[1], d17[1]}, [r0, :32]
vst2.i32 {d16[1], d17[1]}, [r0]
vst2.u16 {d17[1], d19[1]}, [r0]
vst2.f32 {d17[0], d19[0]}, [r0, :64]
ARM VLD1/VST1 (one register, no writeback) assembly parsing and encoding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142583 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-20 15:04:25 +00:00
ARM NEON VLD2/VST2 lane indexed assembly parsing and encoding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146605 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14 23:25:46 +00:00
vst2.8 {d2[4], d3[4]}, [r2], r3
Simplify some NEON assembly pseudo definitions. Let the generic token alias definitions handle the data subtype suffices. We don't need explicit versions for each. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148718 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-23 19:39:08 +00:00
vst2.u8 {d2[4], d3[4]}, [r2]!
vst2.p8 {d2[4], d3[4]}, [r2]
ARM NEON VLD2/VST2 lane indexed assembly parsing and encoding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146605 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14 23:25:46 +00:00
ARM assembly parsing and encoding for VST2 single-element, double spaced. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146990 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 20:46:29 +00:00
vst2.16 {d17[1], d19[1]}, [r0]
vst2.32 {d17[0], d19[0]}, [r0, :64]
Simplify some NEON assembly pseudo definitions. Let the generic token alias definitions handle the data subtype suffices. We don't need explicit versions for each. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148718 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-23 19:39:08 +00:00
vst2.i16 {d7[1], d9[1]}, [r1]!
ARM assembly parsing and encoding for VST2 single-element, double spaced. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146990 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 20:46:29 +00:00
vst2.32 {d6[0], d8[0]}, [r2, :64]!
vst2.16 {d2[1], d4[1]}, [r3], r5
Simplify some NEON assembly pseudo definitions. Let the generic token alias definitions handle the data subtype suffices. We don't need explicit versions for each. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148718 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-23 19:39:08 +00:00
vst2.u32 {d5[0], d7[0]}, [r4, :64], r7
ARM assembly parsing and encoding for VST2 single-element, double spaced. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146990 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 20:46:29 +00:00
ARM enable a few more tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146985 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 20:03:00 +00:00
@ CHECK: vst2.8 {d16[1], d17[1]}, [r0, :16] @ encoding: [0x3f,0x01,0xc0,0xf4]
@ CHECK: vst2.16 {d16[1], d17[1]}, [r0, :32] @ encoding: [0x5f,0x05,0xc0,0xf4]
ARM NEON VLD2/VST2 lane indexed assembly parsing and encoding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146605 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14 23:25:46 +00:00
@ CHECK: vst2.32 {d16[1], d17[1]}, [r0] @ encoding: [0x8f,0x09,0xc0,0xf4]
ARM assembly parsing and encoding for VST2 single-element, double spaced. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146990 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 20:46:29 +00:00
@ CHECK: vst2.16 {d17[1], d19[1]}, [r0] @ encoding: [0x6f,0x15,0xc0,0xf4]
@ CHECK: vst2.32 {d17[0], d19[0]}, [r0, :64] @ encoding: [0x5f,0x19,0xc0,0xf4]
ARM VLD1/VST1 (one register, no writeback) assembly parsing and encoding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142583 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-20 15:04:25 +00:00
ARM NEON VLD2/VST2 lane indexed assembly parsing and encoding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146605 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14 23:25:46 +00:00
@ CHECK: vst2.8 {d2[4], d3[4]}, [r2], r3 @ encoding: [0x83,0x21,0x82,0xf4]
@ CHECK: vst2.8 {d2[4], d3[4]}, [r2]! @ encoding: [0x8d,0x21,0x82,0xf4]
@ CHECK: vst2.8 {d2[4], d3[4]}, [r2] @ encoding: [0x8f,0x21,0x82,0xf4]
ARM assembly parsing and encoding for VST2 single-element, double spaced. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146990 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-20 20:46:29 +00:00
@ CHECK: vst2.16 {d17[1], d19[1]}, [r0] @ encoding: [0x6f,0x15,0xc0,0xf4]
@ CHECK: vst2.32 {d17[0], d19[0]}, [r0, :64] @ encoding: [0x5f,0x19,0xc0,0xf4]
@ CHECK: vst2.16 {d7[1], d9[1]}, [r1]! @ encoding: [0x6d,0x75,0x81,0xf4]
@ CHECK: vst2.32 {d6[0], d8[0]}, [r2, :64]! @ encoding: [0x5d,0x69,0x82,0xf4]
@ CHECK: vst2.16 {d2[1], d4[1]}, [r3], r5 @ encoding: [0x65,0x25,0x83,0xf4]
@ CHECK: vst2.32 {d5[0], d7[0]}, [r4, :64], r7 @ encoding: [0x57,0x59,0x84,0xf4]
ARM VLD1/VST1 (one register, no writeback) assembly parsing and encoding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142583 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-20 15:04:25 +00:00
NEON VST3(single element from one lane) assembly parsing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148755 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-24 00:07:41 +00:00
vst3.8 {d16[1], d17[1], d18[1]}, [r1]
vst3.16 {d6[1], d7[1], d8[1]}, [r2]
vst3.32 {d1[1], d2[1], d3[1]}, [r3]
vst3.u16 {d27[1], d29[1], d31[1]}, [r4]
vst3.i32 {d6[1], d8[1], d10[1]}, [r5]
vst3.i8 {d12[1], d13[1], d14[1]}, [r6], r1
vst3.i16 {d11[1], d12[1], d13[1]}, [r7], r2
vst3.u32 {d2[1], d3[1], d4[1]}, [r8], r3
vst3.u16 {d14[1], d16[1], d18[1]}, [r9], r4
vst3.i32 {d16[1], d18[1], d20[1]}, [r10], r5
vst3.p8 {d6[1], d7[1], d8[1]}, [r8]!
vst3.16 {d9[1], d10[1], d11[1]}, [r7]!
vst3.f32 {d1[1], d2[1], d3[1]}, [r6]!
vst3.p16 {d20[1], d22[1], d24[1]}, [r5]!
vst3.32 {d5[1], d7[1], d9[1]}, [r4]!
@ CHECK: vst3.8 {d16[1], d17[1], d18[1]}, [r1] @ encoding: [0x2f,0x02,0xc1,0xf4]
@ CHECK: vst3.16 {d6[1], d7[1], d8[1]}, [r2] @ encoding: [0x4f,0x66,0x82,0xf4]
@ CHECK: vst3.32 {d1[1], d2[1], d3[1]}, [r3] @ encoding: [0x8f,0x1a,0x83,0xf4]
@ CHECK: vst3.16 {d27[1], d29[1], d31[1]}, [r4] @ encoding: [0x6f,0xb6,0xc4,0xf4]
@ CHECK: vst3.32 {d6[1], d8[1], d10[1]}, [r5] @ encoding: [0xcf,0x6a,0x85,0xf4]
@ CHECK: vst3.8 {d12[1], d13[1], d14[1]}, [r6], r1 @ encoding: [0x21,0xc2,0x86,0xf4]
@ CHECK: vst3.16 {d11[1], d12[1], d13[1]}, [r7], r2 @ encoding: [0x42,0xb6,0x87,0xf4]
@ CHECK: vst3.32 {d2[1], d3[1], d4[1]}, [r8], r3 @ encoding: [0x83,0x2a,0x88,0xf4]
@ CHECK: vst3.16 {d14[1], d16[1], d18[1]}, [r9], r4 @ encoding: [0x64,0xe6,0x89,0xf4]
@ CHECK: vst3.32 {d16[1], d18[1], d20[1]}, [r10], r5 @ encoding: [0xc5,0x0a,0xca,0xf4]
@ CHECK: vst3.8 {d6[1], d7[1], d8[1]}, [r8]! @ encoding: [0x2d,0x62,0x88,0xf4]
@ CHECK: vst3.16 {d9[1], d10[1], d11[1]}, [r7]! @ encoding: [0x4d,0x96,0x87,0xf4]
@ CHECK: vst3.32 {d1[1], d2[1], d3[1]}, [r6]! @ encoding: [0x8d,0x1a,0x86,0xf4]
@ CHECK: vst3.16 {d20[1], d21[1], d22[1]}, [r5]! @ encoding: [0x6d,0x46,0xc5,0xf4]
@ CHECK: vst3.32 {d5[1], d7[1], d9[1]}, [r4]! @ encoding: [0xcd,0x5a,0x84,0xf4]
ARM VLD1/VST1 (one register, no writeback) assembly parsing and encoding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142583 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-20 15:04:25 +00:00
@ vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0, :32]
@ vst4.16 {d16[1], d17[1], d18[1], d19[1]}, [r0]
@ vst4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0, :128]
@ vst4.16 {d17[3], d19[3], d21[3], d23[3]}, [r0, :64]
@ vst4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0]
@ FIXME: vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0, :32] @ encoding: [0x3f,0x03,0xc0,0xf4]
@ FIXME: vst4.16 {d16[1], d17[1], d18[1], d19[1]}, [r0] @ encoding: [0x4f,0x07,0xc0,0xf4]
@ FIXME: vst4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0, :128] @ encoding: [0xaf,0x0b,0xc0,0xf4]
@ FIXME: vst4.16 {d17[3], d19[3], d21[3], d23[3]}, [r0, :64] @ encoding: [0xff,0x17,0xc0,0xf4]
@ FIXME: vst4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0] @ encoding: [0x4f,0x1b,0xc0,0xf4]
ARM parsing datatype suffix variants for non-writeback VST1 instructions. rdar://10435076 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144593 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14 23:43:46 +00:00
@ Spot-check additional size-suffix aliases.
vst1.8 {d2}, [r2]
vst1.p8 {d2}, [r2]
vst1.u8 {d2}, [r2]
vst1.8 {q2}, [r2]
vst1.p8 {q2}, [r2]
vst1.u8 {q2}, [r2]
vst1.f32 {q2}, [r2]
@ CHECK: vst1.8 {d2}, [r2] @ encoding: [0x0f,0x27,0x02,0xf4]
@ CHECK: vst1.8 {d2}, [r2] @ encoding: [0x0f,0x27,0x02,0xf4]
@ CHECK: vst1.8 {d2}, [r2] @ encoding: [0x0f,0x27,0x02,0xf4]
@ CHECK: vst1.8 {d4, d5}, [r2] @ encoding: [0x0f,0x4a,0x02,0xf4]
@ CHECK: vst1.8 {d4, d5}, [r2] @ encoding: [0x0f,0x4a,0x02,0xf4]
@ CHECK: vst1.8 {d4, d5}, [r2] @ encoding: [0x0f,0x4a,0x02,0xf4]
@ CHECK: vst1.32 {d4, d5}, [r2] @ encoding: [0x8f,0x4a,0x02,0xf4]
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