2011-07-11 17:09:57 +00:00
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@ RUN: llvm-mc -triple=armv7-apple-darwin -show-encoding < %s | FileCheck %s
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.syntax unified
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.globl _func
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2011-07-13 17:50:29 +00:00
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@ Check that the assembler can handle the documented syntax from the ARM ARM.
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@ For complex constructs like shifter operands, check more thoroughly for them
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@ once then spot check that following instructions accept the form generally.
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@ This gives us good coverage while keeping the overall size of the test
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@ more reasonable.
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2011-07-11 17:09:57 +00:00
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_func:
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@ CHECK: _func
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2011-07-13 18:12:46 +00:00
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@------------------------------------------------------------------------------
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2011-07-11 17:09:57 +00:00
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@ ADC (immediate)
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2011-07-13 18:12:46 +00:00
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@------------------------------------------------------------------------------
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2011-07-11 17:09:57 +00:00
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adc r1, r2, #0xf
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adc r1, r2, #0xf0
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adc r1, r2, #0xf00
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adc r1, r2, #0xf000
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adc r1, r2, #0xf0000
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adc r1, r2, #0xf00000
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adc r1, r2, #0xf000000
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adc r1, r2, #0xf0000000
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adc r1, r2, #0xf000000f
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adcs r1, r2, #0xf00
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adcseq r1, r2, #0xf00
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2011-07-12 16:25:04 +00:00
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adceq r1, r2, #0xf00
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2011-07-11 17:09:57 +00:00
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@ CHECK: adc r1, r2, #15 @ encoding: [0x0f,0x10,0xa2,0xe2]
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@ CHECK: adc r1, r2, #240 @ encoding: [0xf0,0x10,0xa2,0xe2]
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@ CHECK: adc r1, r2, #3840 @ encoding: [0x0f,0x1c,0xa2,0xe2]
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@ CHECK: adc r1, r2, #61440 @ encoding: [0x0f,0x1a,0xa2,0xe2]
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@ CHECK: adc r1, r2, #983040 @ encoding: [0x0f,0x18,0xa2,0xe2]
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@ CHECK: adc r1, r2, #15728640 @ encoding: [0x0f,0x16,0xa2,0xe2]
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@ CHECK: adc r1, r2, #251658240 @ encoding: [0x0f,0x14,0xa2,0xe2]
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@ CHECK: adc r1, r2, #4026531840 @ encoding: [0x0f,0x12,0xa2,0xe2]
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@ CHECK: adc r1, r2, #4026531855 @ encoding: [0xff,0x12,0xa2,0xe2]
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@ CHECK: adcs r1, r2, #3840 @ encoding: [0x0f,0x1c,0xb2,0xe2]
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@ CHECK: adcseq r1, r2, #3840 @ encoding: [0x0f,0x1c,0xb2,0x02]
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2011-07-12 16:25:04 +00:00
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@ CHECK: adceq r1, r2, #3840 @ encoding: [0x0f,0x1c,0xa2,0x02]
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2011-07-13 17:50:29 +00:00
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2011-07-13 18:12:46 +00:00
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@------------------------------------------------------------------------------
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2011-07-13 17:50:29 +00:00
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@ ADC (register)
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2011-07-13 18:12:46 +00:00
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@ ADC (shifted register)
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@------------------------------------------------------------------------------
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2011-07-13 17:50:29 +00:00
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adc r4, r5, r6
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@ Constant shifts
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adc r4, r5, r6, lsl #1
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adc r4, r5, r6, lsl #31
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adc r4, r5, r6, lsr #1
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adc r4, r5, r6, lsr #31
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adc r4, r5, r6, lsr #32
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adc r4, r5, r6, asr #1
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adc r4, r5, r6, asr #31
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adc r4, r5, r6, asr #32
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adc r4, r5, r6, ror #1
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adc r4, r5, r6, ror #31
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@ Register shifts
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adc r6, r7, r8, lsl r9
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adc r6, r7, r8, lsr r9
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adc r6, r7, r8, asr r9
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adc r6, r7, r8, ror r9
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adc r4, r5, r6, rrx
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2011-07-13 17:57:17 +00:00
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@ Destination register is optional
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adc r5, r6
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adc r4, r5, lsl #1
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adc r4, r5, lsl #31
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adc r4, r5, lsr #1
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adc r4, r5, lsr #31
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adc r4, r5, lsr #32
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adc r4, r5, asr #1
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adc r4, r5, asr #31
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adc r4, r5, asr #32
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adc r4, r5, ror #1
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adc r4, r5, ror #31
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adc r4, r5, rrx
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adc r6, r7, lsl r9
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adc r6, r7, lsr r9
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adc r6, r7, asr r9
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adc r6, r7, ror r9
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adc r4, r5, rrx
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2011-07-13 17:50:29 +00:00
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@ CHECK: adc r4, r5, r6 @ encoding: [0x06,0x40,0xa5,0xe0]
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@ CHECK: adc r4, r5, r6, lsl #1 @ encoding: [0x86,0x40,0xa5,0xe0]
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@ CHECK: adc r4, r5, r6, lsl #31 @ encoding: [0x86,0x4f,0xa5,0xe0]
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@ CHECK: adc r4, r5, r6, lsr #1 @ encoding: [0xa6,0x40,0xa5,0xe0]
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@ CHECK: adc r4, r5, r6, lsr #31 @ encoding: [0xa6,0x4f,0xa5,0xe0]
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@ CHECK: adc r4, r5, r6, lsr #32 @ encoding: [0x26,0x40,0xa5,0xe0]
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@ CHECK: adc r4, r5, r6, asr #1 @ encoding: [0xc6,0x40,0xa5,0xe0]
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@ CHECK: adc r4, r5, r6, asr #31 @ encoding: [0xc6,0x4f,0xa5,0xe0]
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@ CHECK: adc r4, r5, r6, asr #32 @ encoding: [0x46,0x40,0xa5,0xe0]
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@ CHECK: adc r4, r5, r6, ror #1 @ encoding: [0xe6,0x40,0xa5,0xe0]
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@ CHECK: adc r4, r5, r6, ror #31 @ encoding: [0xe6,0x4f,0xa5,0xe0]
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@ CHECK: adc r6, r7, r8, lsl r9 @ encoding: [0x18,0x69,0xa7,0xe0]
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@ CHECK: adc r6, r7, r8, lsr r9 @ encoding: [0x38,0x69,0xa7,0xe0]
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@ CHECK: adc r6, r7, r8, asr r9 @ encoding: [0x58,0x69,0xa7,0xe0]
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@ CHECK: adc r6, r7, r8, ror r9 @ encoding: [0x78,0x69,0xa7,0xe0]
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@ CHECK: adc r4, r5, r6, rrx @ encoding: [0x66,0x40,0xa5,0xe0]
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2011-07-13 17:57:17 +00:00
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@ CHECK: adc r5, r5, r6 @ encoding: [0x06,0x50,0xa5,0xe0]
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@ CHECK: adc r4, r4, r5, lsl #1 @ encoding: [0x85,0x40,0xa4,0xe0]
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@ CHECK: adc r4, r4, r5, lsl #31 @ encoding: [0x85,0x4f,0xa4,0xe0]
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@ CHECK: adc r4, r4, r5, lsr #1 @ encoding: [0xa5,0x40,0xa4,0xe0]
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@ CHECK: adc r4, r4, r5, lsr #31 @ encoding: [0xa5,0x4f,0xa4,0xe0]
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@ CHECK: adc r4, r4, r5, lsr #32 @ encoding: [0x25,0x40,0xa4,0xe0]
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@ CHECK: adc r4, r4, r5, asr #1 @ encoding: [0xc5,0x40,0xa4,0xe0]
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@ CHECK: adc r4, r4, r5, asr #31 @ encoding: [0xc5,0x4f,0xa4,0xe0]
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@ CHECK: adc r4, r4, r5, asr #32 @ encoding: [0x45,0x40,0xa4,0xe0]
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@ CHECK: adc r4, r4, r5, ror #1 @ encoding: [0xe5,0x40,0xa4,0xe0]
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@ CHECK: adc r4, r4, r5, ror #31 @ encoding: [0xe5,0x4f,0xa4,0xe0]
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@ CHECK: adc r4, r4, r5, rrx @ encoding: [0x65,0x40,0xa4,0xe0]
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@ CHECK: adc r6, r6, r7, lsl r9 @ encoding: [0x17,0x69,0xa6,0xe0]
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@ CHECK: adc r6, r6, r7, lsr r9 @ encoding: [0x37,0x69,0xa6,0xe0]
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@ CHECK: adc r6, r6, r7, asr r9 @ encoding: [0x57,0x69,0xa6,0xe0]
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@ CHECK: adc r6, r6, r7, ror r9 @ encoding: [0x77,0x69,0xa6,0xe0]
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@ CHECK: adc r4, r4, r5, rrx @ encoding: [0x65,0x40,0xa4,0xe0]
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2011-07-13 18:12:46 +00:00
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2011-07-13 19:10:23 +00:00
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@------------------------------------------------------------------------------
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@ FIXME: ADR
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@------------------------------------------------------------------------------
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2011-07-13 18:12:46 +00:00
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@------------------------------------------------------------------------------
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@ ADD
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@------------------------------------------------------------------------------
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add r4, r5, #0xf000
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add r4, r5, r6
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add r4, r5, r6, lsl #5
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add r4, r5, r6, lsr #5
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add r4, r5, r6, lsr #5
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add r4, r5, r6, asr #5
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add r4, r5, r6, ror #5
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add r6, r7, r8, lsl r9
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add r6, r7, r8, lsr r9
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add r6, r7, r8, asr r9
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add r6, r7, r8, ror r9
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add r4, r5, r6, rrx
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@ destination register is optional
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add r5, #0xf000
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add r4, r5
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add r4, r5, lsl #5
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add r4, r5, lsr #5
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add r4, r5, lsr #5
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add r4, r5, asr #5
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add r4, r5, ror #5
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add r6, r7, lsl r9
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add r6, r7, lsr r9
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add r6, r7, asr r9
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add r6, r7, ror r9
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add r4, r5, rrx
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@ CHECK: add r4, r5, #61440 @ encoding: [0x0f,0x4a,0x85,0xe2]
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@ CHECK: add r4, r5, r6 @ encoding: [0x06,0x40,0x85,0xe0]
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@ CHECK: add r4, r5, r6, lsl #5 @ encoding: [0x86,0x42,0x85,0xe0]
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@ CHECK: add r4, r5, r6, lsr #5 @ encoding: [0xa6,0x42,0x85,0xe0]
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@ CHECK: add r4, r5, r6, lsr #5 @ encoding: [0xa6,0x42,0x85,0xe0]
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@ CHECK: add r4, r5, r6, asr #5 @ encoding: [0xc6,0x42,0x85,0xe0]
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@ CHECK: add r4, r5, r6, ror #5 @ encoding: [0xe6,0x42,0x85,0xe0]
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@ CHECK: add r6, r7, r8, lsl r9 @ encoding: [0x18,0x69,0x87,0xe0]
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@ CHECK: add r6, r7, r8, lsr r9 @ encoding: [0x38,0x69,0x87,0xe0]
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@ CHECK: add r6, r7, r8, asr r9 @ encoding: [0x58,0x69,0x87,0xe0]
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@ CHECK: add r6, r7, r8, ror r9 @ encoding: [0x78,0x69,0x87,0xe0]
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@ CHECK: add r4, r5, r6, rrx @ encoding: [0x66,0x40,0x85,0xe0]
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@ CHECK: add r5, r5, #61440 @ encoding: [0x0f,0x5a,0x85,0xe2]
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@ CHECK: add r4, r4, r5 @ encoding: [0x05,0x40,0x84,0xe0]
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@ CHECK: add r4, r4, r5, lsl #5 @ encoding: [0x85,0x42,0x84,0xe0]
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@ CHECK: add r4, r4, r5, lsr #5 @ encoding: [0xa5,0x42,0x84,0xe0]
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@ CHECK: add r4, r4, r5, lsr #5 @ encoding: [0xa5,0x42,0x84,0xe0]
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@ CHECK: add r4, r4, r5, asr #5 @ encoding: [0xc5,0x42,0x84,0xe0]
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@ CHECK: add r4, r4, r5, ror #5 @ encoding: [0xe5,0x42,0x84,0xe0]
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@ CHECK: add r6, r6, r7, lsl r9 @ encoding: [0x17,0x69,0x86,0xe0]
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@ CHECK: add r6, r6, r7, lsr r9 @ encoding: [0x37,0x69,0x86,0xe0]
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@ CHECK: add r6, r6, r7, asr r9 @ encoding: [0x57,0x69,0x86,0xe0]
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@ CHECK: add r6, r6, r7, ror r9 @ encoding: [0x77,0x69,0x86,0xe0]
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@ CHECK: add r4, r4, r5, rrx @ encoding: [0x65,0x40,0x84,0xe0]
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2011-07-13 18:55:14 +00:00
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@------------------------------------------------------------------------------
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@ AND
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@------------------------------------------------------------------------------
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and r10, r1, #0xf
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and r10, r1, r6
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and r10, r1, r6, lsl #10
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and r10, r1, r6, lsr #10
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and r10, r1, r6, lsr #10
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and r10, r1, r6, asr #10
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and r10, r1, r6, ror #10
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and r6, r7, r8, lsl r2
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and r6, r7, r8, lsr r2
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and r6, r7, r8, asr r2
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and r6, r7, r8, ror r2
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and r10, r1, r6, rrx
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@ destination register is optional
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and r1, #0xf
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and r10, r1
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and r10, r1, lsl #10
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and r10, r1, lsr #10
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and r10, r1, lsr #10
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and r10, r1, asr #10
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and r10, r1, ror #10
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and r6, r7, lsl r2
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and r6, r7, lsr r2
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and r6, r7, asr r2
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and r6, r7, ror r2
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and r10, r1, rrx
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@ CHECK: and r10, r1, #15 @ encoding: [0x0f,0xa0,0x01,0xe2]
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@ CHECK: and r10, r1, r6 @ encoding: [0x06,0xa0,0x01,0xe0]
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@ CHECK: and r10, r1, r6, lsl #10 @ encoding: [0x06,0xa5,0x01,0xe0]
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@ CHECK: and r10, r1, r6, lsr #10 @ encoding: [0x26,0xa5,0x01,0xe0]
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@ CHECK: and r10, r1, r6, lsr #10 @ encoding: [0x26,0xa5,0x01,0xe0]
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@ CHECK: and r10, r1, r6, asr #10 @ encoding: [0x46,0xa5,0x01,0xe0]
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@ CHECK: and r10, r1, r6, ror #10 @ encoding: [0x66,0xa5,0x01,0xe0]
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|
|
@ CHECK: and r6, r7, r8, lsl r2 @ encoding: [0x18,0x62,0x07,0xe0]
|
|
|
|
|
@ CHECK: and r6, r7, r8, lsr r2 @ encoding: [0x38,0x62,0x07,0xe0]
|
|
|
|
|
@ CHECK: and r6, r7, r8, asr r2 @ encoding: [0x58,0x62,0x07,0xe0]
|
|
|
|
|
@ CHECK: and r6, r7, r8, ror r2 @ encoding: [0x78,0x62,0x07,0xe0]
|
|
|
|
|
@ CHECK: and r10, r1, r6, rrx @ encoding: [0x66,0xa0,0x01,0xe0]
|
|
|
|
|
|
|
|
|
|
@ CHECK: and r1, r1, #15 @ encoding: [0x0f,0x10,0x01,0xe2]
|
|
|
|
|
@ CHECK: and r10, r10, r1 @ encoding: [0x01,0xa0,0x0a,0xe0]
|
|
|
|
|
@ CHECK: and r10, r10, r1, lsl #10 @ encoding: [0x01,0xa5,0x0a,0xe0]
|
|
|
|
|
@ CHECK: and r10, r10, r1, lsr #10 @ encoding: [0x21,0xa5,0x0a,0xe0]
|
|
|
|
|
@ CHECK: and r10, r10, r1, lsr #10 @ encoding: [0x21,0xa5,0x0a,0xe0]
|
|
|
|
|
@ CHECK: and r10, r10, r1, asr #10 @ encoding: [0x41,0xa5,0x0a,0xe0]
|
|
|
|
|
@ CHECK: and r10, r10, r1, ror #10 @ encoding: [0x61,0xa5,0x0a,0xe0]
|
|
|
|
|
@ CHECK: and r6, r6, r7, lsl r2 @ encoding: [0x17,0x62,0x06,0xe0]
|
|
|
|
|
@ CHECK: and r6, r6, r7, lsr r2 @ encoding: [0x37,0x62,0x06,0xe0]
|
|
|
|
|
@ CHECK: and r6, r6, r7, asr r2 @ encoding: [0x57,0x62,0x06,0xe0]
|
|
|
|
|
@ CHECK: and r6, r6, r7, ror r2 @ encoding: [0x77,0x62,0x06,0xe0]
|
|
|
|
|
@ CHECK: and r10, r10, r1, rrx @ encoding: [0x61,0xa0,0x0a,0xe0]
|
|
|
|
|
|
2011-07-13 19:10:23 +00:00
|
|
|
@------------------------------------------------------------------------------
|
|
|
|
|
@ FIXME: ASR
|
|
|
|
|
@------------------------------------------------------------------------------
|
|
|
|
|
@------------------------------------------------------------------------------
|
|
|
|
|
@ FIXME: B
|
|
|
|
|
@------------------------------------------------------------------------------
|
|
|
|
|
@------------------------------------------------------------------------------
|
|
|
|
|
@ FIXME: BFC
|
|
|
|
|
@------------------------------------------------------------------------------
|
|
|
|
|
@------------------------------------------------------------------------------
|
|
|
|
|
@ FIXME: BFI
|
|
|
|
|
@------------------------------------------------------------------------------
|
2011-07-13 19:12:32 +00:00
|
|
|
|
|
|
|
|
@------------------------------------------------------------------------------
|
2011-07-13 19:16:30 +00:00
|
|
|
@ BIC
|
2011-07-13 19:12:32 +00:00
|
|
|
@------------------------------------------------------------------------------
|
|
|
|
|
bic r10, r1, #0xf
|
|
|
|
|
bic r10, r1, r6
|
|
|
|
|
bic r10, r1, r6, lsl #10
|
|
|
|
|
bic r10, r1, r6, lsr #10
|
|
|
|
|
bic r10, r1, r6, lsr #10
|
|
|
|
|
bic r10, r1, r6, asr #10
|
|
|
|
|
bic r10, r1, r6, ror #10
|
|
|
|
|
bic r6, r7, r8, lsl r2
|
|
|
|
|
bic r6, r7, r8, lsr r2
|
|
|
|
|
bic r6, r7, r8, asr r2
|
|
|
|
|
bic r6, r7, r8, ror r2
|
|
|
|
|
bic r10, r1, r6, rrx
|
|
|
|
|
|
|
|
|
|
@ destination register is optional
|
|
|
|
|
bic r1, #0xf
|
|
|
|
|
bic r10, r1
|
|
|
|
|
bic r10, r1, lsl #10
|
|
|
|
|
bic r10, r1, lsr #10
|
|
|
|
|
bic r10, r1, lsr #10
|
|
|
|
|
bic r10, r1, asr #10
|
|
|
|
|
bic r10, r1, ror #10
|
|
|
|
|
bic r6, r7, lsl r2
|
|
|
|
|
bic r6, r7, lsr r2
|
|
|
|
|
bic r6, r7, asr r2
|
|
|
|
|
bic r6, r7, ror r2
|
|
|
|
|
bic r10, r1, rrx
|
|
|
|
|
|
|
|
|
|
@ CHECK: bic r10, r1, #15 @ encoding: [0x0f,0xa0,0xc1,0xe3]
|
|
|
|
|
@ CHECK: bic r10, r1, r6 @ encoding: [0x06,0xa0,0xc1,0xe1]
|
|
|
|
|
@ CHECK: bic r10, r1, r6, lsl #10 @ encoding: [0x06,0xa5,0xc1,0xe1]
|
|
|
|
|
@ CHECK: bic r10, r1, r6, lsr #10 @ encoding: [0x26,0xa5,0xc1,0xe1]
|
|
|
|
|
@ CHECK: bic r10, r1, r6, lsr #10 @ encoding: [0x26,0xa5,0xc1,0xe1]
|
|
|
|
|
@ CHECK: bic r10, r1, r6, asr #10 @ encoding: [0x46,0xa5,0xc1,0xe1]
|
|
|
|
|
@ CHECK: bic r10, r1, r6, ror #10 @ encoding: [0x66,0xa5,0xc1,0xe1]
|
|
|
|
|
@ CHECK: bic r6, r7, r8, lsl r2 @ encoding: [0x18,0x62,0xc7,0xe1]
|
|
|
|
|
@ CHECK: bic r6, r7, r8, lsr r2 @ encoding: [0x38,0x62,0xc7,0xe1]
|
|
|
|
|
@ CHECK: bic r6, r7, r8, asr r2 @ encoding: [0x58,0x62,0xc7,0xe1]
|
|
|
|
|
@ CHECK: bic r6, r7, r8, ror r2 @ encoding: [0x78,0x62,0xc7,0xe1]
|
|
|
|
|
@ CHECK: bic r10, r1, r6, rrx @ encoding: [0x66,0xa0,0xc1,0xe1]
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
@ CHECK: bic r1, r1, #15 @ encoding: [0x0f,0x10,0xc1,0xe3]
|
|
|
|
|
@ CHECK: bic r10, r10, r1 @ encoding: [0x01,0xa0,0xca,0xe1]
|
|
|
|
|
@ CHECK: bic r10, r10, r1, lsl #10 @ encoding: [0x01,0xa5,0xca,0xe1]
|
|
|
|
|
@ CHECK: bic r10, r10, r1, lsr #10 @ encoding: [0x21,0xa5,0xca,0xe1]
|
|
|
|
|
@ CHECK: bic r10, r10, r1, lsr #10 @ encoding: [0x21,0xa5,0xca,0xe1]
|
|
|
|
|
@ CHECK: bic r10, r10, r1, asr #10 @ encoding: [0x41,0xa5,0xca,0xe1]
|
|
|
|
|
@ CHECK: bic r10, r10, r1, ror #10 @ encoding: [0x61,0xa5,0xca,0xe1]
|
|
|
|
|
@ CHECK: bic r6, r6, r7, lsl r2 @ encoding: [0x17,0x62,0xc6,0xe1]
|
|
|
|
|
@ CHECK: bic r6, r6, r7, lsr r2 @ encoding: [0x37,0x62,0xc6,0xe1]
|
|
|
|
|
@ CHECK: bic r6, r6, r7, asr r2 @ encoding: [0x57,0x62,0xc6,0xe1]
|
|
|
|
|
@ CHECK: bic r6, r6, r7, ror r2 @ encoding: [0x77,0x62,0xc6,0xe1]
|
|
|
|
|
@ CHECK: bic r10, r10, r1, rrx @ encoding: [0x61,0xa0,0xca,0xe1]
|
|
|
|
|
|
2011-07-13 19:17:36 +00:00
|
|
|
@------------------------------------------------------------------------------
|
|
|
|
|
@ BKPT
|
|
|
|
|
@------------------------------------------------------------------------------
|
|
|
|
|
bkpt #10
|
|
|
|
|
bkpt #65535
|
|
|
|
|
|
2011-07-13 20:10:10 +00:00
|
|
|
@ CHECK: bkpt #10 @ encoding: [0x7a,0x00,0x20,0xe1]
|
|
|
|
|
@ CHECK: bkpt #65535 @ encoding: [0x7f,0xff,0x2f,0xe1]
|
2011-07-13 20:11:04 +00:00
|
|
|
|
|
|
|
|
@------------------------------------------------------------------------------
|
|
|
|
|
@ BL/BLX (immediate)
|
|
|
|
|
@------------------------------------------------------------------------------
|
|
|
|
|
|
|
|
|
|
bl _bar
|
|
|
|
|
@ FIXME: blx _bar
|
|
|
|
|
|
2011-07-13 20:25:46 +00:00
|
|
|
@ CHECK: bl _bar @ encoding: [A,A,A,0xeb]
|
|
|
|
|
@ CHECK: @ fixup A - offset: 0, value: _bar, kind: fixup_arm_uncondbranch
|
|
|
|
|
|
|
|
|
|
@------------------------------------------------------------------------------
|
|
|
|
|
@ BLX (register)
|
|
|
|
|
@------------------------------------------------------------------------------
|
2011-07-13 20:11:04 +00:00
|
|
|
blx r2
|
|
|
|
|
blxne r2
|
|
|
|
|
|
|
|
|
|
@ CHECK: blx r2 @ encoding: [0x32,0xff,0x2f,0xe1]
|
|
|
|
|
@ CHECK: blxne r2 @ encoding: [0x32,0xff,0x2f,0x11]
|
|
|
|
|
|
2011-07-13 20:25:46 +00:00
|
|
|
@------------------------------------------------------------------------------
|
|
|
|
|
@ BX
|
|
|
|
|
@------------------------------------------------------------------------------
|
|
|
|
|
|
|
|
|
|
bx r2
|
|
|
|
|
bxne r2
|
|
|
|
|
|
|
|
|
|
@ CHECK: bx r2 @ encoding: [0x12,0xff,0x2f,0xe1]
|
|
|
|
|
@ CHECK: bxne r2 @ encoding: [0x12,0xff,0x2f,0x11]
|
|
|
|
|
|
|
|
|
|
@------------------------------------------------------------------------------
|
|
|
|
|
@ BXJ
|
|
|
|
|
@------------------------------------------------------------------------------
|
|
|
|
|
|
|
|
|
|
bxj r2
|
|
|
|
|
bxjne r2
|
2011-07-13 20:11:04 +00:00
|
|
|
|
2011-07-13 20:25:46 +00:00
|
|
|
@ CHECK: bxj r2 @ encoding: [0x22,0xff,0x2f,0xe1]
|
|
|
|
|
@ CHECK: bxjne r2 @ encoding: [0x22,0xff,0x2f,0x11]
|
2011-07-13 22:01:08 +00:00
|
|
|
|
|
|
|
|
@------------------------------------------------------------------------------
|
|
|
|
|
@ FIXME: CBNZ/CBZ
|
|
|
|
|
@------------------------------------------------------------------------------
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
@------------------------------------------------------------------------------
|
|
|
|
|
@ CDP/CDP2
|
|
|
|
|
@------------------------------------------------------------------------------
|
2011-07-13 22:19:10 +00:00
|
|
|
cdp p7, #1, c1, c1, c1, #4
|
|
|
|
|
cdp2 p7, #1, c1, c1, c1, #4
|
2011-07-13 22:01:08 +00:00
|
|
|
|
2011-07-13 22:19:10 +00:00
|
|
|
@ CHECK: cdp p7, #1, c1, c1, c1, #4 @ encoding: [0x81,0x17,0x11,0xee]
|
|
|
|
|
@ CHECK: cdp2 p7, #1, c1, c1, c1, #4 @ encoding: [0x81,0x17,0x11,0xfe]
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
@------------------------------------------------------------------------------
|
|
|
|
|
@ CLREX
|
|
|
|
|
@------------------------------------------------------------------------------
|
|
|
|
|
clrex
|
|
|
|
|
|
|
|
|
|
@ CHECK: clrex @ encoding: [0x1f,0xf0,0x7f,0xf5]
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
@------------------------------------------------------------------------------
|
|
|
|
|
@ CLZ
|
|
|
|
|
@------------------------------------------------------------------------------
|
|
|
|
|
clz r1, r2
|
|
|
|
|
clzeq r1, r2
|
|
|
|
|
|
|
|
|
|
@ CHECK: clz r1, r2 @ encoding: [0x12,0x1f,0x6f,0xe1]
|
|
|
|
|
@ CHECK: clzeq r1, r2 @ encoding: [0x12,0x1f,0x6f,0x01]
|
2011-07-13 22:26:58 +00:00
|
|
|
|
|
|
|
|
@------------------------------------------------------------------------------
|
|
|
|
|
@ CMN
|
|
|
|
|
@------------------------------------------------------------------------------
|
|
|
|
|
cmn r1, #0xf
|
|
|
|
|
cmn r1, r6
|
|
|
|
|
cmn r1, r6, lsl #10
|
|
|
|
|
cmn r1, r6, lsr #10
|
|
|
|
|
cmn sp, r6, lsr #10
|
|
|
|
|
cmn r1, r6, asr #10
|
|
|
|
|
cmn r1, r6, ror #10
|
|
|
|
|
cmn r7, r8, lsl r2
|
|
|
|
|
cmn sp, r8, lsr r2
|
|
|
|
|
cmn r7, r8, asr r2
|
|
|
|
|
cmn r7, r8, ror r2
|
|
|
|
|
cmn r1, r6, rrx
|
|
|
|
|
|
|
|
|
|
@ CHECK: cmn r1, #15 @ encoding: [0x0f,0x00,0x71,0xe3]
|
|
|
|
|
@ CHECK: cmn r1, r6 @ encoding: [0x06,0x00,0x71,0xe1]
|
|
|
|
|
@ CHECK: cmn r1, r6, lsl #10 @ encoding: [0x06,0x05,0x71,0xe1]
|
|
|
|
|
@ CHECK: cmn r1, r6, lsr #10 @ encoding: [0x26,0x05,0x71,0xe1]
|
|
|
|
|
@ CHECK: cmn sp, r6, lsr #10 @ encoding: [0x26,0x05,0x7d,0xe1]
|
|
|
|
|
@ CHECK: cmn r1, r6, asr #10 @ encoding: [0x46,0x05,0x71,0xe1]
|
|
|
|
|
@ CHECK: cmn r1, r6, ror #10 @ encoding: [0x66,0x05,0x71,0xe1]
|
|
|
|
|
@ CHECK: cmn r7, r8, lsl r2 @ encoding: [0x18,0x02,0x77,0xe1]
|
|
|
|
|
@ CHECK: cmn sp, r8, lsr r2 @ encoding: [0x38,0x02,0x7d,0xe1]
|
|
|
|
|
@ CHECK: cmn r7, r8, asr r2 @ encoding: [0x58,0x02,0x77,0xe1]
|
|
|
|
|
@ CHECK: cmn r7, r8, ror r2 @ encoding: [0x78,0x02,0x77,0xe1]
|
|
|
|
|
@ CHECK: cmn r1, r6, rrx @ encoding: [0x66,0x00,0x71,0xe1]
|
|
|
|
|
|
|
|
|
|
@------------------------------------------------------------------------------
|
|
|
|
|
@ CMP
|
|
|
|
|
@------------------------------------------------------------------------------
|
|
|
|
|
cmp r1, #0xf
|
|
|
|
|
cmp r1, r6
|
|
|
|
|
cmp r1, r6, lsl #10
|
|
|
|
|
cmp r1, r6, lsr #10
|
|
|
|
|
cmp sp, r6, lsr #10
|
|
|
|
|
cmp r1, r6, asr #10
|
|
|
|
|
cmp r1, r6, ror #10
|
|
|
|
|
cmp r7, r8, lsl r2
|
|
|
|
|
cmp sp, r8, lsr r2
|
|
|
|
|
cmp r7, r8, asr r2
|
|
|
|
|
cmp r7, r8, ror r2
|
|
|
|
|
cmp r1, r6, rrx
|
|
|
|
|
|
|
|
|
|
@ CHECK: cmp r1, #15 @ encoding: [0x0f,0x00,0x51,0xe3]
|
|
|
|
|
@ CHECK: cmp r1, r6 @ encoding: [0x06,0x00,0x51,0xe1]
|
|
|
|
|
@ CHECK: cmp r1, r6, lsl #10 @ encoding: [0x06,0x05,0x51,0xe1]
|
|
|
|
|
@ CHECK: cmp r1, r6, lsr #10 @ encoding: [0x26,0x05,0x51,0xe1]
|
|
|
|
|
@ CHECK: cmp sp, r6, lsr #10 @ encoding: [0x26,0x05,0x5d,0xe1]
|
|
|
|
|
@ CHECK: cmp r1, r6, asr #10 @ encoding: [0x46,0x05,0x51,0xe1]
|
|
|
|
|
@ CHECK: cmp r1, r6, ror #10 @ encoding: [0x66,0x05,0x51,0xe1]
|
|
|
|
|
@ CHECK: cmp r7, r8, lsl r2 @ encoding: [0x18,0x02,0x57,0xe1]
|
|
|
|
|
@ CHECK: cmp sp, r8, lsr r2 @ encoding: [0x38,0x02,0x5d,0xe1]
|
|
|
|
|
@ CHECK: cmp r7, r8, asr r2 @ encoding: [0x58,0x02,0x57,0xe1]
|
|
|
|
|
@ CHECK: cmp r7, r8, ror r2 @ encoding: [0x78,0x02,0x57,0xe1]
|
|
|
|
|
@ CHECK: cmp r1, r6, rrx @ encoding: [0x66,0x00,0x51,0xe1]
|
|
|
|
|
|
