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llvm-6502/test/MC/Disassembler/ARM/basic-arm-instructions-v8.txt

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[ARMv8] Add some missing tests for DSB/DMB. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190060 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-05 16:05:45 +00:00
# RUN: llvm-mc -disassemble -triple armv8 -mattr=+db -show-encoding < %s | FileCheck %s
Add AArch32 DCPS{1,2,3} and HLT instructions. These were pretty straightforward instructions, with some assembly support required for HLT. The ARM assembler is keen to split the instruction mnemonic into a (non-existent) 'H' instruction with the LT condition code. An exception for HLT is needed. HLT follows the same rules as BKPT when in IT blocks, so the special BKPT hadling code has been adapted to handle HLT also. Regression tests added including diagnostic tests for out of range immediates and illegal condition codes, as well as negative tests for pre-ARMv8. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190053 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-05 14:14:19 +00:00
# New v8 ARM instructions
# HLT
0x70 0x00 0x00 0xe1
# CHECK: hlt #0
0x7f 0xff 0x0f 0xe1
# CHECK: hlt #65535
[ARMv8] Add some missing tests for DSB/DMB. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190060 91177308-0d34-0410-b5e6-96231b3b80d8
2013-09-05 16:05:45 +00:00
0x59 0xf0 0x7f 0xf5
0x51 0xf0 0x7f 0xf5
0x55 0xf0 0x7f 0xf5
0x5d 0xf0 0x7f 0xf5
# CHECK: dmb ishld
# CHECK: dmb oshld
# CHECK: dmb nshld
# CHECK: dmb ld
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