llvm-6502/test/MC/ARM/neon-vswp.s

@ RUN: llvm-mc -mcpu=cortex-a8 -triple armv7-apple-darwin -show-encoding < %s | FileCheck %s

vswp d1, d2
vswp q1, q2

@ CHECK: vswp	d1, d2                  @ encoding: [0x02,0x10,0xb2,0xf3]
@ CHECK: vswp	q1, q2                  @ encoding: [0x44,0x20,0xb2,0xf3]
ARM encoding for VSWP got the second operand incorrect. Make the non-tied register operand names line up with what the base class encoding handler expects. rdar://11157236 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153766 91177308-0d34-0410-b5e6-96231b3b80d8 2012-03-30 18:53:01 +00:00			`@ RUN: llvm-mc -mcpu=cortex-a8 -triple armv7-apple-darwin -show-encoding < %s \| FileCheck %s`

			`vswp d1, d2`
			`vswp q1, q2`

			`@ CHECK: vswp d1, d2 @ encoding: [0x02,0x10,0xb2,0xf3]`
			`@ CHECK: vswp q1, q2 @ encoding: [0x44,0x20,0xb2,0xf3]`