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llvm-6502/test/MC/X86/intel-syntax.s

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Add new test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148128 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-13 18:45:31 +00:00
// RUN: llvm-mc -triple x86_64-unknown-unknown -x86-asm-syntax=intel %s | FileCheck %s
Intel syntax: Ignore mnemonic aliases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148316 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-17 18:30:45 +00:00
_test:
xor EAX, EAX
ret
_main:
Add new test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148128 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-13 18:45:31 +00:00
// CHECK: movl $257, -4(%rsp)
mov DWORD PTR [RSP - 4], 257
Intel syntax: Do not unncessarily create plus expression for memory operand displacement. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148321 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-17 19:08:07 +00:00
// CHECK: movl $258, 4(%rsp)
mov DWORD PTR [RSP + 4], 258
Add new test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148128 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-13 18:45:31 +00:00
// CHECK: movq $123, -16(%rsp)
mov QWORD PTR [RSP - 16], 123
// CHECK: movb $97, -17(%rsp)
mov BYTE PTR [RSP - 17], 97
// CHECK: movl -4(%rsp), %eax
mov EAX, DWORD PTR [RSP - 4]
Intel syntax: Robustify memory operand parsing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148312 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-17 18:00:18 +00:00
// CHECK: movq (%rsp), %rax
mov RAX, QWORD PTR [RSP]
// CHECK: movl $-4, -4(%rsp)
mov DWORD PTR [RSP - 4], -4
// CHECK: movq 0, %rcx
mov RCX, QWORD PTR [0]
// CHECK: movl -24(%rsp,%rax,4), %eax
mov EAX, DWORD PTR [RSP + 4*RAX - 24]
Intel syntax: Parse "BYTE PTR [RDX + RCX]" git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148334 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-17 21:25:10 +00:00
// CHECK: movb %dil, (%rdx,%rcx)
mov BYTE PTR [RDX + RCX], DIL
Intel syntax: Fix parser match class to check memory operand size. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148338 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-17 21:48:03 +00:00
// CHECK: movzwl 2(%rcx), %edi
movzx EDI, WORD PTR [RCX + 2]
Intel syntax: Ignore mnemonic aliases. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148316 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-17 18:30:45 +00:00
// CHECK: callq _test
call _test
Process instructions after match to select alternative encoding which may be more desirable. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148431 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-18 22:42:29 +00:00
// CHECK: andw $12, %ax
and ax, 12
// CHECK: andw $-12, %ax
and ax, -12
// CHECK: andw $257, %ax
and ax, 257
// CHECK: andw $-257, %ax
and ax, -257
// CHECK: andl $12, %eax
and eax, 12
// CHECK: andl $-12, %eax
and eax, -12
// CHECK: andl $257, %eax
and eax, 257
// CHECK: andl $-257, %eax
and eax, -257
// CHECK: andq $12, %rax
and rax, 12
// CHECK: andq $-12, %rax
and rax, -12
// CHECK: andq $257, %rax
and rax, 257
// CHECK: andq $-257, %rax
and rax, -257
Intel syntax: Robustify register parsing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148591 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-20 22:32:05 +00:00
// CHECK: fld %st(0)
fld ST(0)
Intel syntax: Parse segment registers. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148712 91177308-0d34-0410-b5e6-96231b3b80d8
2012-01-23 18:31:58 +00:00
// CHECK: movl %fs:(%rdi), %eax
[ms-inline asm] Extend support for parsing Intel bracketed memory operands that have an arbitrary ordering of the base register, index register and displacement. rdar://12527141 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172484 91177308-0d34-0410-b5e6-96231b3b80d8
2013-01-14 22:31:35 +00:00
mov EAX, DWORD PTR FS:[RDI]
// CHECK: leal (,%rdi,4), %r8d
lea R8D, DWORD PTR [4*RDI]
// CHECK: movl _fnan(,%ecx,4), %ecx
mov ECX, DWORD PTR [4*ECX + _fnan]
// CHECK: movq %fs:320, %rax
mov RAX, QWORD PTR FS:[320]
// CHECK: vpgatherdd %xmm8, (%r15,%xmm9,2), %xmm1
vpgatherdd XMM10, DWORD PTR [R15 + 2*XMM9], XMM8
// CHECK: movsd -8, %xmm5
movsd XMM5, QWORD PTR [-8]
// CHECK: movl %ecx, (%eax)
mov [eax], ecx
// CHECK: movl %ecx, (,%ebx,4)
mov [4*ebx], ecx
// CHECK: movl %ecx, (,%ebx,4)
mov [ebx*4], ecx
// CHECK: movl %ecx, 1024
mov [1024], ecx
// CHECK: movl %ecx, 4132
mov [0x1024], ecx
// CHECK: movl %ecx, 32
mov [16 + 16], ecx
// CHECK: movl %ecx, 0
mov [16 - 16], ecx
// CHECK: movl %ecx, 32
mov [16][16], ecx
// CHECK: movl %ecx, (%eax,%ebx,4)
mov [eax + 4*ebx], ecx
// CHECK: movl %ecx, (%eax,%ebx,4)
mov [eax + ebx*4], ecx
// CHECK: movl %ecx, (%eax,%ebx,4)
mov [4*ebx + eax], ecx
// CHECK: movl %ecx, (%eax,%ebx,4)
mov [ebx*4 + eax], ecx
// CHECK: movl %ecx, (%eax,%ebx,4)
mov [eax][4*ebx], ecx
// CHECK: movl %ecx, (%eax,%ebx,4)
mov [eax][ebx*4], ecx
// CHECK: movl %ecx, (%eax,%ebx,4)
mov [4*ebx][eax], ecx
// CHECK: movl %ecx, (%eax,%ebx,4)
mov [ebx*4][eax], ecx
// CHECK: movl %ecx, 12(%eax)
mov [eax + 12], ecx
// CHECK: movl %ecx, 12(%eax)
mov [12 + eax], ecx
// CHECK: movl %ecx, 32(%eax)
mov [eax + 16 + 16], ecx
// CHECK: movl %ecx, 32(%eax)
mov [16 + eax + 16], ecx
// CHECK: movl %ecx, 32(%eax)
mov [16 + 16 + eax], ecx
// CHECK: movl %ecx, 12(%eax)
mov [eax][12], ecx
// CHECK: movl %ecx, 12(%eax)
mov [12][eax], ecx
// CHECK: movl %ecx, 32(%eax)
mov [eax][16 + 16], ecx
// CHECK: movl %ecx, 32(%eax)
mov [eax + 16][16], ecx
// CHECK: movl %ecx, 32(%eax)
mov [eax][16][16], ecx
// CHECK: movl %ecx, 32(%eax)
mov [16][eax + 16], ecx
// CHECK: movl %ecx, 32(%eax)
mov [16 + eax][16], ecx
// CHECK: movl %ecx, 32(%eax)
mov [16][16 + eax], ecx
// CHECK: movl %ecx, 32(%eax)
mov [16 + 16][eax], ecx
// CHECK: movl %ecx, 32(%eax)
mov [eax][16][16], ecx
// CHECK: movl %ecx, 32(%eax)
mov [16][eax][16], ecx
// CHECK: movl %ecx, 32(%eax)
mov [16][16][eax], ecx
// CHECK: movl %ecx, 16(,%ebx,4)
mov [4*ebx + 16], ecx
// CHECK: movl %ecx, 16(,%ebx,4)
mov [ebx*4 + 16], ecx
// CHECK: movl %ecx, 16(,%ebx,4)
mov [4*ebx][16], ecx
// CHECK: movl %ecx, 16(,%ebx,4)
mov [ebx*4][16], ecx
// CHECK: movl %ecx, 16(,%ebx,4)
mov [16 + 4*ebx], ecx
// CHECK: movl %ecx, 16(,%ebx,4)
mov [16 + ebx*4], ecx
// CHECK: movl %ecx, 16(,%ebx,4)
mov [16][4*ebx], ecx
// CHECK: movl %ecx, 16(,%ebx,4)
mov [16][ebx*4], ecx
// CHECK: movl %ecx, 16(%eax,%ebx,4)
mov [eax + 4*ebx + 16], ecx
// CHECK: movl %ecx, 16(%eax,%ebx,4)
mov [eax + 16 + 4*ebx], ecx
// CHECK: movl %ecx, 16(%eax,%ebx,4)
mov [4*ebx + eax + 16], ecx
// CHECK: movl %ecx, 16(%eax,%ebx,4)
mov [4*ebx + 16 + eax], ecx
// CHECK: movl %ecx, 16(%eax,%ebx,4)
mov [16 + eax + 4*ebx], ecx
// CHECK: movl %ecx, 16(%eax,%ebx,4)
mov [16 + eax + 4*ebx], ecx
// CHECK: movl %ecx, 16(%eax,%ebx,4)
mov [eax][4*ebx + 16], ecx
// CHECK: movl %ecx, 16(%eax,%ebx,4)
mov [eax][16 + 4*ebx], ecx
// CHECK: movl %ecx, 16(%eax,%ebx,4)
mov [4*ebx][eax + 16], ecx
// CHECK: movl %ecx, 16(%eax,%ebx,4)
mov [4*ebx][16 + eax], ecx
// CHECK: movl %ecx, 16(%eax,%ebx,4)
mov [16][eax + 4*ebx], ecx
// CHECK: movl %ecx, 16(%eax,%ebx,4)
mov [16][eax + 4*ebx], ecx
// CHECK: movl %ecx, 16(%eax,%ebx,4)
mov [eax + 4*ebx][16], ecx
// CHECK: movl %ecx, 16(%eax,%ebx,4)
mov [eax + 16][4*ebx], ecx
// CHECK: movl %ecx, 16(%eax,%ebx,4)
mov [4*ebx + eax][16], ecx
// CHECK: movl %ecx, 16(%eax,%ebx,4)
mov [4*ebx + 16][eax], ecx
// CHECK: movl %ecx, 16(%eax,%ebx,4)
mov [16 + eax][4*ebx], ecx
// CHECK: movl %ecx, 16(%eax,%ebx,4)
mov [16 + eax][4*ebx], ecx
// CHECK: movl %ecx, 16(%eax,%ebx,4)
mov [eax][4*ebx][16], ecx
// CHECK: movl %ecx, 16(%eax,%ebx,4)
mov [eax][16][4*ebx], ecx
// CHECK: movl %ecx, 16(%eax,%ebx,4)
mov [4*ebx][eax][16], ecx
// CHECK: movl %ecx, 16(%eax,%ebx,4)
mov [4*ebx][16][eax], ecx
// CHECK: movl %ecx, 16(%eax,%ebx,4)
mov [16][eax][4*ebx], ecx
// CHECK: movl %ecx, 16(%eax,%ebx,4)
mov [16][eax][4*ebx], ecx
// CHECK: movl %ecx, 16(%eax,%ebx,4)
mov [eax + ebx*4 + 16], ecx
// CHECK: movl %ecx, 16(%eax,%ebx,4)
mov [eax + 16 + ebx*4], ecx
// CHECK: movl %ecx, 16(%eax,%ebx,4)
mov [ebx*4 + eax + 16], ecx
// CHECK: movl %ecx, 16(%eax,%ebx,4)
mov [ebx*4 + 16 + eax], ecx
// CHECK: movl %ecx, 16(%eax,%ebx,4)
mov [16 + eax + ebx*4], ecx
// CHECK: movl %ecx, 16(%eax,%ebx,4)
mov [16 + eax + ebx*4], ecx
// CHECK: movl %ecx, 16(%eax,%ebx,4)
mov [eax][ebx*4 + 16], ecx
// CHECK: movl %ecx, 16(%eax,%ebx,4)
mov [eax][16 + ebx*4], ecx
// CHECK: movl %ecx, 16(%eax,%ebx,4)
mov [ebx*4][eax + 16], ecx
// CHECK: movl %ecx, 16(%eax,%ebx,4)
mov [ebx*4][16 + eax], ecx
// CHECK: movl %ecx, 16(%eax,%ebx,4)
mov [16][eax + ebx*4], ecx
// CHECK: movl %ecx, 16(%eax,%ebx,4)
mov [16][eax + ebx*4], ecx
// CHECK: movl %ecx, 16(%eax,%ebx,4)
mov [eax + ebx*4][16], ecx
// CHECK: movl %ecx, 16(%eax,%ebx,4)
mov [eax + 16][ebx*4], ecx
// CHECK: movl %ecx, 16(%eax,%ebx,4)
mov [ebx*4 + eax][16], ecx
// CHECK: movl %ecx, 16(%eax,%ebx,4)
mov [ebx*4 + 16][eax], ecx
// CHECK: movl %ecx, 16(%eax,%ebx,4)
mov [16 + eax][ebx*4], ecx
// CHECK: movl %ecx, 16(%eax,%ebx,4)
mov [16 + eax][ebx*4], ecx
// CHECK: movl %ecx, 16(%eax,%ebx,4)
mov [eax][ebx*4][16], ecx
// CHECK: movl %ecx, 16(%eax,%ebx,4)
mov [eax][16][ebx*4], ecx
// CHECK: movl %ecx, 16(%eax,%ebx,4)
mov [ebx*4][eax][16], ecx
// CHECK: movl %ecx, 16(%eax,%ebx,4)
mov [ebx*4][16][eax], ecx
// CHECK: movl %ecx, 16(%eax,%ebx,4)
mov [16][eax][ebx*4], ecx
// CHECK: movl %ecx, 16(%eax,%ebx,4)
mov [16][eax][ebx*4], ecx
// CHECK: movl %ecx, -16(%eax,%ebx,4)
mov [eax][ebx*4 - 16], ecx
[ms-inline asm] Add support for numeric displacement expressions in bracketed memory operands. Essentially, this layers an infix calculator on top of the parsing state machine. The scale on the index register is still expected to be an immediate __asm mov eax, [eax + ebx*4] and will not work with more complex expressions. For example, __asm mov eax, [eax + ebx*(2*2)] The plus and minus binary operators assume the numeric value of a register is zero so as to not change the displacement. Register operands should never be an operand for a multiply or divide operation; the scale*indexreg expression is always replaced with a zero on the operand stack to prevent such a case. rdar://13521380 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178881 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-05 16:28:55 +00:00
// CHECK: prefetchnta 12800(%esi)
prefetchnta [esi + (200*64)]
// CHECK: prefetchnta 32(%esi)
prefetchnta [esi + (64/2)]
// CHECK: prefetchnta 128(%esi)
prefetchnta [esi + (64/2*4)]
// CHECK: prefetchnta 8(%esi)
prefetchnta [esi + (64/(2*4))]
// CHECK: prefetchnta 48(%esi)
prefetchnta [esi + (64/(2*4)+40)]
// CHECK: movl %ecx, -16(%eax,%ebx,4)
mov [eax][ebx*4 - 2*8], ecx
// CHECK: movl %ecx, -16(%eax,%ebx,4)
mov [eax][4*ebx - 2*8], ecx
// CHECK: movl %ecx, -16(%eax,%ebx,4)
mov [eax + 4*ebx - 2*8], ecx
// CHECK: movl %ecx, -16(%eax,%ebx,4)
mov [12 + eax + (4*ebx) - 2*14], ecx
// CHECK: movl %ecx, -16(%eax,%ebx,4)
mov [eax][ebx*4 - 2*2*2*2], ecx
// CHECK: movl %ecx, -16(%eax,%ebx,4)
mov [eax][ebx*4 - (2*8)], ecx
// CHECK: movl %ecx, -16(%eax,%ebx,4)
mov [eax][ebx*4 - 2 * 8 + 4 - 4], ecx
// CHECK: movl %ecx, -16(%eax,%ebx,4)
mov [eax + ebx*4 - 2 * 8 + 4 - 4], ecx
// CHECK: movl %ecx, -16(%eax,%ebx,4)
mov [eax + ebx*4 - 2 * ((8 + 4) - 4)], ecx
// CHECK: movl %ecx, -16(%eax,%ebx,4)
mov [-2 * ((8 + 4) - 4) + eax + ebx*4], ecx
// CHECK: movl %ecx, -16(%eax,%ebx,4)
mov [((-2) * ((8 + 4) - 4)) + eax + ebx*4], ecx
// CHECK: movl %ecx, -16(%eax,%ebx,4)
mov [eax + ((-2) * ((8 + 4) - 4)) + ebx*4], ecx
ret
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