llvm-6502/test/MC/Mips/cfi.s

# RUN: llvm-mc %s -triple=mips-unknown-unknown -show-encoding -mcpu=mips32 | \
# RUN:     FileCheck %s
# RUN: llvm-mc %s -triple=mips64-unknown-unknown -show-encoding -mcpu=mips64 | \
# RUN:     FileCheck %s

# Check that we can accept register names in CFI directives and that they are
# canonicalised to their DWARF register numbers.

        .cfi_startproc         # CHECK: .cfi_startproc
        .cfi_register   $6, $5 # CHECK: .cfi_register 6, 5
        .cfi_def_cfa    $fp, 8 # CHECK: .cfi_def_cfa 30, 8
        .cfi_def_cfa    $2, 16 # CHECK: .cfi_def_cfa 2, 16
        .cfi_endproc           # CHECK: .cfi_endproc
[mips] Rewrite MipsAsmParser and MipsOperand. Summary: Highlights: - Registers are resolved much later (by the render method). Prior to that point, GPR32's/GPR64's are GPR's regardless of register size. Similarly FGR32's/FGR64's/AFGR64's are FGR's regardless of register size or FR mode. Numeric registers can be anything. - All registers are parsed the same way everywhere (even when handling symbol aliasing) - One consequence is that all registers can be specified numerically almost anywhere (e.g. $fccX, $wX). The exception is symbol aliasing but that can be easily resolved. - Removes the need for the hasConsumedDollar hack - Parenthesis and Bracket suffixes are handled generically - Micromips instructions are parsed directly instead of going through the standard encodings first. - rdhwr accepts all 32 registers, and the following instructions that previously xfailed now work: ddiv, ddivu, div, divu, cvt.l.[ds], se[bh], wsbh, floor.w.[ds], c.ngl.d, c.sf.s, dsbh, dshd, madd.s, msub.s, nmadd.s, nmsub.s, swxc1 - Diagnostics involving registers point at the correct character (the $) - There's only one kind of immediate in MipsOperand. LSA immediates are handled by the predicate and renderer. Lowlights: - Hardcoded '$zero' in the div patterns is handled with a hack. MipsOperand::isReg() will return true for a k_RegisterIndex token with Index == 0 and getReg() will return ZERO for this case. Note that it doesn't return ZERO_64 on isGP64() targets. - I haven't cleaned up all of the now-unused functions. Some more of the generic parser could be removed too (integers and relocs for example). - insve.df needed a custom decoder to handle the implicit fourth operand that was needed to make it parse correctly. The difficulty was that the matcher expected a Token<'0'> but gets an Imm<0>. Adding an implicit zero solved this. Reviewers: matheusalmeida, vmedic Reviewed By: matheusalmeida Differential Revision: http://llvm-reviews.chandlerc.com/D3222 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205292 91177308-0d34-0410-b5e6-96231b3b80d8 2014-04-01 10:35:28 +00:00			`# RUN: llvm-mc %s -triple=mips-unknown-unknown -show-encoding -mcpu=mips32 \| \`
			`# RUN: FileCheck %s`
			`# RUN: llvm-mc %s -triple=mips64-unknown-unknown -show-encoding -mcpu=mips64 \| \`
			`# RUN: FileCheck %s`

			`# Check that we can accept register names in CFI directives and that they are`
			`# canonicalised to their DWARF register numbers.`

			`.cfi_startproc # CHECK: .cfi_startproc`
			`.cfi_register $6, $5 # CHECK: .cfi_register 6, 5`
			`.cfi_def_cfa $fp, 8 # CHECK: .cfi_def_cfa 30, 8`
			`.cfi_def_cfa $2, 16 # CHECK: .cfi_def_cfa 2, 16`
			`.cfi_endproc # CHECK: .cfi_endproc`