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llvm-6502/test/MC/X86/x86-32.s

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rip out the 'heinous' x86 MCCodeEmitter implementation. We still have the templated X86 JIT emitter, *and* the almost-copy in X86InstrInfo for getting instruction sizes. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96059 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-13 00:49:29 +00:00
// RUN: llvm-mc -triple i386-unknown-unknown --show-encoding %s | FileCheck %s
fix the encodings of monitor and mwait, which were completely busted in both encoders. I'm not bothering to fix it in the old one at this point. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95947 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-12 01:06:22 +00:00
Define the x86 pause instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104204 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 01:35:50 +00:00
pause
// CHECK: pause
// CHECK: encoding: [0xf3,0x90]
Fix the sfence instruction to use MRM_F8 instead of MRM7r, since it doesn't have a register operand. Also, use I instead of PSI, for consistency with mfence and lfence. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104203 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 01:23:41 +00:00
sfence
// CHECK: sfence
// CHECK: encoding: [0x0f,0xae,0xf8]
fix the encodings of monitor and mwait, which were completely busted in both encoders. I'm not bothering to fix it in the old one at this point. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95947 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-12 01:06:22 +00:00
lfence
// CHECK: lfence
// CHECK: encoding: [0x0f,0xae,0xe8]
mfence
// CHECK: mfence
// CHECK: encoding: [0x0f,0xae,0xf0]
monitor
// CHECK: monitor
Recognize monitor/mwait with explicit register arguments git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125805 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-18 00:48:11 +00:00
// CHECK: encoding: [0x0f,0x01,0xc8]
monitor %eax, %ecx, %edx
// CHECK: monitor
fix the encodings of monitor and mwait, which were completely busted in both encoders. I'm not bothering to fix it in the old one at this point. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95947 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-12 01:06:22 +00:00
// CHECK: encoding: [0x0f,0x01,0xc8]
mwait
// CHECK: mwait
Recognize monitor/mwait with explicit register arguments git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@125805 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-18 00:48:11 +00:00
// CHECK: encoding: [0x0f,0x01,0xc9]
mwait %eax, %ecx
// CHECK: mwait
remove special cases for vmlaunch, vmresume, vmxoff, and swapgs fix swapgs to be spelled right. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96058 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-13 00:41:14 +00:00
// CHECK: encoding: [0x0f,0x01,0xc9]
vmcall
// CHECK: vmcall
// CHECK: encoding: [0x0f,0x01,0xc1]
Add vmfunc instruction to X86 assembler and disassembler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150899 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-19 01:39:49 +00:00
vmfunc
// CHECK: vmfunc
// CHECK: encoding: [0x0f,0x01,0xd4]
remove special cases for vmlaunch, vmresume, vmxoff, and swapgs fix swapgs to be spelled right. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96058 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-13 00:41:14 +00:00
vmlaunch
// CHECK: vmlaunch
// CHECK: encoding: [0x0f,0x01,0xc2]
vmresume
// CHECK: vmresume
// CHECK: encoding: [0x0f,0x01,0xc3]
vmxoff
// CHECK: vmxoff
// CHECK: encoding: [0x0f,0x01,0xc4]
swapgs
// CHECK: swapgs
// CHECK: encoding: [0x0f,0x01,0xf8]
MC/AsmParser: Attempt to constant fold expressions up-front. This ensures we avoid fixups for obvious cases like '-(16)'. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96064 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-13 01:28:07 +00:00
Add X86 assembler and disassembler support for AMD SVM instructions. Original patch by Kay Tiong Khoo. Few tweaks by me for code density and to reduce replication. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150873 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-18 08:19:49 +00:00
vmrun %eax
// CHECK: vmrun %eax
// CHECK: encoding: [0x0f,0x01,0xd8]
vmmcall
// CHECK: vmmcall
// CHECK: encoding: [0x0f,0x01,0xd9]
vmload %eax
// CHECK: vmload %eax
// CHECK: encoding: [0x0f,0x01,0xda]
vmsave %eax
// CHECK: vmsave %eax
// CHECK: encoding: [0x0f,0x01,0xdb]
stgi
// CHECK: stgi
// CHECK: encoding: [0x0f,0x01,0xdc]
clgi
// CHECK: clgi
// CHECK: encoding: [0x0f,0x01,0xdd]
skinit %eax
// CHECK: skinit %eax
// CHECK: encoding: [0x0f,0x01,0xde]
invlpga %ecx, %eax
// CHECK: invlpga %ecx, %eax
// CHECK: encoding: [0x0f,0x01,0xdf]
rdtscp
add encoder support and tests for rdtscp git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96076 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-13 03:42:24 +00:00
// CHECK: rdtscp
// CHECK: encoding: [0x0f,0x01,0xf9]
MC/AsmParser: Attempt to constant fold expressions up-front. This ensures we avoid fixups for obvious cases like '-(16)'. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96064 91177308-0d34-0410-b5e6-96231b3b80d8
2010-02-13 01:28:07 +00:00
// CHECK: movl %eax, 16(%ebp) # encoding: [0x89,0x45,0x10]
movl %eax, 16(%ebp)
// CHECK: movl %eax, -16(%ebp) # encoding: [0x89,0x45,0xf0]
movl %eax, -16(%ebp)
X86: Fix encoding for TEST{8,16,32}rr. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97982 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-08 21:10:36 +00:00
// CHECK: testb %bl, %cl # encoding: [0x84,0xcb]
testb %bl, %cl
MC/X86: Rename alternate spellings of CMP{8,16,32} and mark as "code gen only" so they don't get selected by the asm matcher. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98097 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-09 22:50:40 +00:00
// CHECK: cmpl %eax, %ebx # encoding: [0x39,0xc3]
cmpl %eax, %ebx
MC/X86: Rename alternate spellings of ADD{8,16,32} and mark as "code gen only" so they don't get selected by the asm matcher. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98098 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-09 22:50:46 +00:00
// CHECK: addw %ax, %ax # encoding: [0x66,0x01,0xc0]
addw %ax, %ax
MC/X86: Add temporary hack to match shrl $1,%eax correctly, to support testing other functionality on 403.gcc compiled at -O0. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98405 91177308-0d34-0410-b5e6-96231b3b80d8
2010-03-13 00:47:29 +00:00
// CHECK: shrl %eax # encoding: [0xd1,0xe8]
shrl $1, %eax
fix the encoding of the obscure "moffset" forms of moves, i386 part first. rdar://7947184 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103660 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-12 22:48:24 +00:00
fix an encoding mismatch where "sal %eax, 1" was not using the short encoding for shl. Caught by inspection. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117820 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30 18:13:10 +00:00
// CHECK: shll %eax # encoding: [0xd1,0xe0]
sall $1, %eax
// CHECK: shll %eax # encoding: [0xd1,0xe0]
sal $1, %eax
fix the encoding of the obscure "moffset" forms of moves, i386 part first. rdar://7947184 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103660 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-12 22:48:24 +00:00
// moffset forms of moves, rdar://7947184
Updated the llvm-mc disassembler C API to support for the X86 target. rdar://10873652 As part of this I updated the llvm-mc disassembler C API to always call the SymbolLookUp call back even if there is no getOpInfo call back. If there is a getOpInfo call back that is tried first and then if that gets no information then the SymbolLookUp is called. I also made the code more robust by memset(3)'ing to zero the LLVMOpInfo1 struct before then setting SymbolicOp.Value before for the call to getOpInfo. And also don't use any values from the LLVMOpInfo1 struct if getOpInfo returns 0. And also don't use any of the ReferenceType or ReferenceName values from SymbolLookUp if it returns NULL. rdar://10873563 and rdar://10873683 For the X86 target also fixed bugs so the annotations get printed. Also fixed a few places in the ARM target that was not producing symbolic operands for some instructions. rdar://10878166 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151267 91177308-0d34-0410-b5e6-96231b3b80d8
2012-02-23 18:18:17 +00:00
movb 0, %al // CHECK: movb 0, %al # encoding: [0xa0,0x00,0x00,0x00,0x00]
movw 0, %ax // CHECK: movw 0, %ax # encoding: [0x66,0xa1,0x00,0x00,0x00,0x00]
movl 0, %eax // CHECK: movl 0, %eax # encoding: [0xa1,0x00,0x00,0x00,0x00]
fix the encoding of the obscure "moffset" forms of moves, i386 part first. rdar://7947184 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103660 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-12 22:48:24 +00:00
Fix so "int3" is correctly accepted, added "into" and fixed "int" with an argument, like "int $4", to not get an Assertion error. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@103791 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-14 19:16:02 +00:00
// rdar://7973775
into
// CHECK: into
// CHECK: encoding: [0xce]
int3
// CHECK: int3
// CHECK: encoding: [0xcc]
int $4
// CHECK: int $4
// CHECK: encoding: [0xcd,0x04]
int $255
// CHECK: int $255
// CHECK: encoding: [0xcd,0xff]
Fix assembly parsing and encoding of the pushf and popf family of instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104231 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-20 16:16:00 +00:00
// CHECK: pushfl # encoding: [0x9c]
pushf
// CHECK: pushfl # encoding: [0x9c]
pushfl
// CHECK: popfl # encoding: [0x9d]
popf
// CHECK: popfl # encoding: [0x9d]
popfl
Added retl for 32-bit x86 and added retq for 64-bit x86. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104394 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-21 23:01:38 +00:00
// rdar://8014869
retl
// CHECK: ret
// CHECK: encoding: [0xc3]
MC/X86: Add aliases for CMOVcc variants. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104549 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24 20:32:23 +00:00
// rdar://7973854
// CHECK: cmoval %eax, %edx
// CHECK: encoding: [0x0f,0x47,0xd0]
cmoval %eax,%edx
// CHECK: cmovael %eax, %edx
// CHECK: encoding: [0x0f,0x43,0xd0]
cmovael %eax,%edx
// CHECK: cmovbel %eax, %edx
// CHECK: encoding: [0x0f,0x46,0xd0]
cmovbel %eax,%edx
// CHECK: cmovbl %eax, %edx
// CHECK: encoding: [0x0f,0x42,0xd0]
cmovbl %eax,%edx
add a missed cmov alias, part of rdar://8416805 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113693 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-11 17:08:22 +00:00
// CHECK: cmovbw %bx, %bx
cmovnae %bx,%bx
MC/X86: Add aliases for CMOVcc variants. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104549 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-24 20:32:23 +00:00
// CHECK: cmovbel %eax, %edx
// CHECK: encoding: [0x0f,0x46,0xd0]
cmovbel %eax,%edx
// CHECK: cmovbl %eax, %edx
// CHECK: encoding: [0x0f,0x42,0xd0]
cmovcl %eax,%edx
// CHECK: cmovel %eax, %edx
// CHECK: encoding: [0x0f,0x44,0xd0]
cmovel %eax,%edx
// CHECK: cmovgl %eax, %edx
// CHECK: encoding: [0x0f,0x4f,0xd0]
cmovgl %eax,%edx
// CHECK: cmovgel %eax, %edx
// CHECK: encoding: [0x0f,0x4d,0xd0]
cmovgel %eax,%edx
// CHECK: cmovll %eax, %edx
// CHECK: encoding: [0x0f,0x4c,0xd0]
cmovll %eax,%edx
// CHECK: cmovlel %eax, %edx
// CHECK: encoding: [0x0f,0x4e,0xd0]
cmovlel %eax,%edx
// CHECK: cmovbel %eax, %edx
// CHECK: encoding: [0x0f,0x46,0xd0]
cmovnal %eax,%edx
// CHECK: cmovnel %eax, %edx
// CHECK: encoding: [0x0f,0x45,0xd0]
cmovnel %eax,%edx
// CHECK: cmovael %eax, %edx
// CHECK: encoding: [0x0f,0x43,0xd0]
cmovnbl %eax,%edx
// CHECK: cmoval %eax, %edx
// CHECK: encoding: [0x0f,0x47,0xd0]
cmovnbel %eax,%edx
// CHECK: cmovael %eax, %edx
// CHECK: encoding: [0x0f,0x43,0xd0]
cmovncl %eax,%edx
// CHECK: cmovnel %eax, %edx
// CHECK: encoding: [0x0f,0x45,0xd0]
cmovnel %eax,%edx
// CHECK: cmovlel %eax, %edx
// CHECK: encoding: [0x0f,0x4e,0xd0]
cmovngl %eax,%edx
// CHECK: cmovgel %eax, %edx
// CHECK: encoding: [0x0f,0x4d,0xd0]
cmovnl %eax,%edx
// CHECK: cmovnel %eax, %edx
// CHECK: encoding: [0x0f,0x45,0xd0]
cmovnel %eax,%edx
// CHECK: cmovlel %eax, %edx
// CHECK: encoding: [0x0f,0x4e,0xd0]
cmovngl %eax,%edx
// CHECK: cmovll %eax, %edx
// CHECK: encoding: [0x0f,0x4c,0xd0]
cmovngel %eax,%edx
// CHECK: cmovgel %eax, %edx
// CHECK: encoding: [0x0f,0x4d,0xd0]
cmovnll %eax,%edx
// CHECK: cmovgl %eax, %edx
// CHECK: encoding: [0x0f,0x4f,0xd0]
cmovnlel %eax,%edx
// CHECK: cmovnol %eax, %edx
// CHECK: encoding: [0x0f,0x41,0xd0]
cmovnol %eax,%edx
// CHECK: cmovnpl %eax, %edx
// CHECK: encoding: [0x0f,0x4b,0xd0]
cmovnpl %eax,%edx
// CHECK: cmovnsl %eax, %edx
// CHECK: encoding: [0x0f,0x49,0xd0]
cmovnsl %eax,%edx
// CHECK: cmovnel %eax, %edx
// CHECK: encoding: [0x0f,0x45,0xd0]
cmovnzl %eax,%edx
// CHECK: cmovol %eax, %edx
// CHECK: encoding: [0x0f,0x40,0xd0]
cmovol %eax,%edx
// CHECK: cmovpl %eax, %edx
// CHECK: encoding: [0x0f,0x4a,0xd0]
cmovpl %eax,%edx
// CHECK: cmovsl %eax, %edx
// CHECK: encoding: [0x0f,0x48,0xd0]
cmovsl %eax,%edx
// CHECK: cmovel %eax, %edx
// CHECK: encoding: [0x0f,0x44,0xd0]
cmovzl %eax,%edx
MC/X86: Define explicit immediate forms of cmp{ss,sd,ps,pd}. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104622 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 18:40:53 +00:00
// CHECK: cmpps $0, %xmm0, %xmm1
// CHECK: encoding: [0x0f,0xc2,0xc8,0x00]
cmpps $0, %xmm0, %xmm1
// CHECK: cmpps $0, (%eax), %xmm1
// CHECK: encoding: [0x0f,0xc2,0x08,0x00]
cmpps $0, 0(%eax), %xmm1
// CHECK: cmppd $0, %xmm0, %xmm1
// CHECK: encoding: [0x66,0x0f,0xc2,0xc8,0x00]
cmppd $0, %xmm0, %xmm1
// CHECK: cmppd $0, (%eax), %xmm1
// CHECK: encoding: [0x66,0x0f,0xc2,0x08,0x00]
cmppd $0, 0(%eax), %xmm1
// CHECK: cmpss $0, %xmm0, %xmm1
// CHECK: encoding: [0xf3,0x0f,0xc2,0xc8,0x00]
cmpss $0, %xmm0, %xmm1
// CHECK: cmpss $0, (%eax), %xmm1
// CHECK: encoding: [0xf3,0x0f,0xc2,0x08,0x00]
cmpss $0, 0(%eax), %xmm1
// CHECK: cmpsd $0, %xmm0, %xmm1
// CHECK: encoding: [0xf2,0x0f,0xc2,0xc8,0x00]
cmpsd $0, %xmm0, %xmm1
// CHECK: cmpsd $0, (%eax), %xmm1
// CHECK: encoding: [0xf2,0x0f,0xc2,0x08,0x00]
cmpsd $0, 0(%eax), %xmm1
MC/X86: Add a hack to allow recognizing 'cmpltps' and friends. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104626 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 19:49:32 +00:00
// Check matching of instructions which embed the SSE comparison code.
// CHECK: cmpps $0, %xmm0, %xmm1
// CHECK: encoding: [0x0f,0xc2,0xc8,0x00]
cmpeqps %xmm0, %xmm1
// CHECK: cmppd $1, %xmm0, %xmm1
// CHECK: encoding: [0x66,0x0f,0xc2,0xc8,0x01]
cmpltpd %xmm0, %xmm1
// CHECK: cmpss $2, %xmm0, %xmm1
// CHECK: encoding: [0xf3,0x0f,0xc2,0xc8,0x02]
cmpless %xmm0, %xmm1
// CHECK: cmppd $3, %xmm0, %xmm1
// CHECK: encoding: [0x66,0x0f,0xc2,0xc8,0x03]
cmpunordpd %xmm0, %xmm1
// CHECK: cmpps $4, %xmm0, %xmm1
// CHECK: encoding: [0x0f,0xc2,0xc8,0x04]
cmpneqps %xmm0, %xmm1
// CHECK: cmppd $5, %xmm0, %xmm1
// CHECK: encoding: [0x66,0x0f,0xc2,0xc8,0x05]
cmpnltpd %xmm0, %xmm1
// CHECK: cmpss $6, %xmm0, %xmm1
// CHECK: encoding: [0xf3,0x0f,0xc2,0xc8,0x06]
cmpnless %xmm0, %xmm1
// CHECK: cmpsd $7, %xmm0, %xmm1
// CHECK: encoding: [0xf2,0x0f,0xc2,0xc8,0x07]
cmpordsd %xmm0, %xmm1
Changed the encoding of X86 floating point stack operations where both operands are st(0). These can be encoded using an opcode for storing in st(0) or using an opcode for storing in st(i), where i can also be 0. To allow testing with the darwin assembler and get a matching binary the opcode for storing in st(0) is now used. To do this the same logical trick is use from the darwin assembler in converting things like this: fmul %st(0), %st into this: fmul %st(0) by looking for the second operand being X86::ST0 for specific floating point mnemonics then removing the second X86::ST0 operand. This also has the add benefit to allow things like: fmul %st(1), %st that llvm-mc did not assemble. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104634 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-25 20:52:34 +00:00
// rdar://7995856
// CHECK: fmul %st(0)
// CHECK: encoding: [0xd8,0xc8]
fmul %st(0), %st
// CHECK: fadd %st(0)
// CHECK: encoding: [0xd8,0xc0]
fadd %st(0), %st
// CHECK: fsub %st(0)
// CHECK: encoding: [0xd8,0xe0]
fsub %st(0), %st
// CHECK: fsubr %st(0)
// CHECK: encoding: [0xd8,0xe8]
fsubr %st(0), %st
// CHECK: fdivr %st(0)
// CHECK: encoding: [0xd8,0xf8]
fdivr %st(0), %st
// CHECK: fdiv %st(0)
// CHECK: encoding: [0xd8,0xf0]
fdiv %st(0), %st
Fix the x86 move to/from segment register instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104731 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-26 20:10:45 +00:00
// radr://8017519
// CHECK: movl %cs, %eax
// CHECK: encoding: [0x8c,0xc8]
movl %cs, %eax
// CHECK: movw %cs, %ax
// CHECK: encoding: [0x66,0x8c,0xc8]
movw %cs, %ax
// CHECK: movl %cs, (%eax)
// CHECK: encoding: [0x8c,0x08]
movl %cs, (%eax)
// CHECK: movw %cs, (%eax)
// CHECK: encoding: [0x66,0x8c,0x08]
movw %cs, (%eax)
// CHECK: movl %eax, %cs
// CHECK: encoding: [0x8e,0xc8]
movl %eax, %cs
// CHECK: movl (%eax), %cs
// CHECK: encoding: [0x8e,0x08]
movl (%eax), %cs
// CHECK: movw (%eax), %cs
// CHECK: encoding: [0x66,0x8e,0x08]
movw (%eax), %cs
Fix the use of x86 control and debug registers so that the assertion failure in getX86RegNum() does not happen. Patch by Shantonu Sen! git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104994 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-28 19:01:27 +00:00
// radr://8033374
// CHECK: movl %cr0, %eax
// CHECK: encoding: [0x0f,0x20,0xc0]
movl %cr0,%eax
// CHECK: movl %cr1, %eax
// CHECK: encoding: [0x0f,0x20,0xc8]
movl %cr1,%eax
// CHECK: movl %cr2, %eax
// CHECK: encoding: [0x0f,0x20,0xd0]
movl %cr2,%eax
// CHECK: movl %cr3, %eax
// CHECK: encoding: [0x0f,0x20,0xd8]
movl %cr3,%eax
// CHECK: movl %cr4, %eax
// CHECK: encoding: [0x0f,0x20,0xe0]
movl %cr4,%eax
// CHECK: movl %dr0, %eax
// CHECK: encoding: [0x0f,0x21,0xc0]
movl %dr0,%eax
// CHECK: movl %dr1, %eax
// CHECK: encoding: [0x0f,0x21,0xc8]
movl %dr1,%eax
// CHECK: movl %dr1, %eax
// CHECK: encoding: [0x0f,0x21,0xc8]
movl %dr1,%eax
// CHECK: movl %dr2, %eax
// CHECK: encoding: [0x0f,0x21,0xd0]
movl %dr2,%eax
// CHECK: movl %dr3, %eax
// CHECK: encoding: [0x0f,0x21,0xd8]
movl %dr3,%eax
// CHECK: movl %dr4, %eax
// CHECK: encoding: [0x0f,0x21,0xe0]
movl %dr4,%eax
// CHECK: movl %dr5, %eax
// CHECK: encoding: [0x0f,0x21,0xe8]
movl %dr5,%eax
// CHECK: movl %dr6, %eax
// CHECK: encoding: [0x0f,0x21,0xf0]
movl %dr6,%eax
// CHECK: movl %dr7, %eax
// CHECK: encoding: [0x0f,0x21,0xf8]
movl %dr7,%eax
MC/X86: Add alias for fwait. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105001 91177308-0d34-0410-b5e6-96231b3b80d8
2010-05-28 20:59:10 +00:00
// radr://8017522
// CHECK: wait
// CHECK: encoding: [0x9b]
fwait
fix rdar://7873482 by teaching the instruction encoder to emit segment prefixes. Daniel wrote most of this patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106364 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-19 00:34:00 +00:00
// rdar://7873482
Allow x86 mov instructions to/from memory with absolute address to be encoded and disassembled with a segment override prefix. Fixes PR16962. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199364 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-16 07:36:58 +00:00
// CHECK: [0x65,0xa1,0x7c,0x00,0x00,0x00]
fix rdar://7873482 by teaching the instruction encoder to emit segment prefixes. Daniel wrote most of this patch. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106364 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-19 00:34:00 +00:00
movl %gs:124, %eax
Add support for the x86 instructions "pusha" and "popa". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106671 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-23 20:00:58 +00:00
Allow x86 mov instructions to/from memory with absolute address to be encoded and disassembled with a segment override prefix. Fixes PR16962. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199364 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-16 07:36:58 +00:00
// CHECK: [0x65,0xa3,0x7c,0x00,0x00,0x00]
movl %eax, %gs:124
[x86] Add PUSHA16,POPA16 instructions, and fix aliases for 16-bit mode git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198753 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-08 12:57:45 +00:00
// CHECK: pushal
Add support for the x86 instructions "pusha" and "popa". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106671 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-23 20:00:58 +00:00
// CHECK: encoding: [0x60]
pusha
[x86] Add PUSHA16,POPA16 instructions, and fix aliases for 16-bit mode git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198753 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-08 12:57:45 +00:00
// CHECK: popal
Add support for the x86 instructions "pusha" and "popa". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106671 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-23 20:00:58 +00:00
// CHECK: encoding: [0x61]
popa
[x86] Add PUSHA16,POPA16 instructions, and fix aliases for 16-bit mode git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198753 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-08 12:57:45 +00:00
// CHECK: pushaw
// CHECK: encoding: [0x66,0x60]
pushaw
// CHECK: popaw
// CHECK: encoding: [0x66,0x61]
popaw
Add support for the x86 instructions "pusha" and "popa". git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106671 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-23 20:00:58 +00:00
// CHECK: pushal
// CHECK: encoding: [0x60]
pushal
// CHECK: popal
// CHECK: encoding: [0x61]
popal
X86: Mark JMP{32,64}[mr] as requires 32-bit/64-bit mode. They are the same instruction, we only want to allow the one for the current subtarget. - This also fixes suffix matching for jmp instructions, because it eliminates the ambiguity between 'jmpl' and 'jmpq'. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108746 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-19 20:44:16 +00:00
// CHECK: jmpl *8(%eax)
// CHECK: encoding: [0xff,0x60,0x08]
jmp *8(%eax)
fix PR7465, mishandling of lcall and ljmp: intersegment long call and jumps. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111496 91177308-0d34-0410-b5e6-96231b3b80d8
2010-08-19 01:18:43 +00:00
// PR7465
// CHECK: lcalll $2, $4660
// CHECK: encoding: [0x9a,0x34,0x12,0x00,0x00,0x02,0x00]
lcalll $0x2, $0x1234
fix the encoding of the "jump on *cx" family of instructions, rdar://8061602 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113343 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-08 04:30:51 +00:00
// rdar://8061602
L1:
jcxz L1
// CHECK: jcxz L1
// CHECK: encoding: [0x67,0xe3,A]
jecxz L1
// CHECK: jecxz L1
// CHECK: encoding: [0xe3,A]
implement the iret suite of instructions properly, fixing rdar://8403974 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113349 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-08 05:38:31 +00:00
// rdar://8403974
iret
// CHECK: iretl
// CHECK: encoding: [0xcf]
iretw
// CHECK: iretw
// CHECK: encoding: [0x66,0xcf]
iretl
// CHECK: iretl
// CHECK: encoding: [0xcf]
implement proper support for sysret{,l,q}, rdar://8403907 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113350 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-08 05:45:34 +00:00
// rdar://8403907
sysret
// CHECK: sysretl
// CHECK: encoding: [0x0f,0x07]
sysretl
// CHECK: sysretl
// CHECK: encoding: [0x0f,0x07]
add support for the commuted form of the test instruction, rdar://8018260. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113352 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-08 05:51:12 +00:00
// rdar://8018260
testl %ecx, -24(%ebp)
// CHECK: testl -24(%ebp), %ecx
testl -24(%ebp), %ecx
// CHECK: testl -24(%ebp), %ecx
fix bugs in push/pop segment support, rdar://8407242 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113422 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-08 22:13:08 +00:00
// rdar://8407242
push %cs
// CHECK: pushl %cs
// CHECK: encoding: [0x0e]
push %ds
// CHECK: pushl %ds
// CHECK: encoding: [0x1e]
push %ss
// CHECK: pushl %ss
// CHECK: encoding: [0x16]
push %es
// CHECK: pushl %es
// CHECK: encoding: [0x06]
push %fs
// CHECK: pushl %fs
// CHECK: encoding: [0x0f,0xa0]
push %gs
// CHECK: pushl %gs
// CHECK: encoding: [0x0f,0xa8]
pushw %cs
// CHECK: pushw %cs
// CHECK: encoding: [0x66,0x0e]
pushw %ds
// CHECK: pushw %ds
// CHECK: encoding: [0x66,0x1e]
pushw %ss
// CHECK: pushw %ss
// CHECK: encoding: [0x66,0x16]
pushw %es
// CHECK: pushw %es
// CHECK: encoding: [0x66,0x06]
pushw %fs
// CHECK: pushw %fs
// CHECK: encoding: [0x66,0x0f,0xa0]
pushw %gs
// CHECK: pushw %gs
// CHECK: encoding: [0x66,0x0f,0xa8]
pop %ss
// CHECK: popl %ss
// CHECK: encoding: [0x17]
pop %ds
// CHECK: popl %ds
// CHECK: encoding: [0x1f]
pop %es
// CHECK: popl %es
// CHECK: encoding: [0x07]
add support for pushfd/popfd which are aliases for pushfl/popfl. This fixes rdar://8408129 - pushfd and popfd get invalid instruction mnemonic errors git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113690 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-11 16:39:16 +00:00
// rdar://8408129
pushfd
// CHECK: pushfl
popfd
// CHECK: popfl
pushfl
// CHECK: pushfl
popfl
// CHECK: popfl
add support for all the setCC aliases. Part of rdar://8416805 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113692 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-11 17:06:05 +00:00
// rdar://8416805
setc %bl
setnae %bl
setnb %bl
setnc %bl
setna %bl
setnbe %bl
setpe %bl
setpo %bl
setnge %bl
setnl %bl
setng %bl
setnle %bl
apparently jmpl $1,$2 is an alias for ljmpl, similiarly for call. Add this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113948 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15 05:25:21 +00:00
fix PR8686, accepting a 'b' suffix at the end of all the setcc instructions. I choose to handle this with an asmparser hack, though it could be handled by changing all the instruction definitions to allow be "setneb" instead of "setne". The asm parser hack is better in this case, because we want the disassembler to produce setne, not setneb. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120260 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-28 20:23:50 +00:00
// PR8686
setneb %cl // CHECK: setne %cl
setcb %bl // CHECK: setb %bl
setnaeb %bl // CHECK: setb %bl
apparently jmpl $1,$2 is an alias for ljmpl, similiarly for call. Add this. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113948 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15 05:25:21 +00:00
// CHECK: lcalll $31438, $31438
// CHECK: lcalll $31438, $31438
// CHECK: ljmpl $31438, $31438
// CHECK: ljmpl $31438, $31438
calll $0x7ace,$0x7ace
lcalll $0x7ace,$0x7ace
jmpl $0x7ace,$0x7ace
ljmpl $0x7ace,$0x7ace
[x86] Add JMP16[rm],CALL16[rm] instructions, and fix up aliases git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198754 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-08 12:57:49 +00:00
// CHECK: lcallw $31438, $31438
// CHECK: lcallw $31438, $31438
// CHECK: ljmpw $31438, $31438
// CHECK: ljmpw $31438, $31438
callw $0x7ace,$0x7ace
lcallw $0x7ace,$0x7ace
jmpw $0x7ace,$0x7ace
ljmpw $0x7ace,$0x7ace
lcall and ljmp always default to lcalll and ljmpl. This finally wraps up r8418316 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@113949 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-15 05:30:20 +00:00
// CHECK: lcalll $31438, $31438
// CHECK: lcalll $31438, $31438
// CHECK: ljmpl $31438, $31438
// CHECK: ljmpl $31438, $31438
call $0x7ace,$0x7ace
lcall $0x7ace,$0x7ace
jmp $0x7ace,$0x7ace
ljmp $0x7ace,$0x7ace
Fix an inconsistency in the x86 backend that led it to reject "calll foo" on x86-32: 32-bit calls were named "call" not "calll". 64-bit calls were correctly named "callq", so this only impacted x86-32. This fixes rdar://8456370 - llvm-mc rejects 'calll' This also exposes that mingw/64 is generating a 32-bit call instead of a 64-bit call, I will file a bugzilla. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114534 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-22 05:49:14 +00:00
// rdar://8456370
// CHECK: calll a
calll a
merge and clean up tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115177 91177308-0d34-0410-b5e6-96231b3b80d8
2010-09-30 17:24:05 +00:00
// CHECK: incb %al # encoding: [0xfe,0xc0]
incb %al
// CHECK: incw %ax # encoding: [0x66,0x40]
incw %ax
// CHECK: incl %eax # encoding: [0x40]
incl %eax
// CHECK: decb %al # encoding: [0xfe,0xc8]
decb %al
// CHECK: decw %ax # encoding: [0x66,0x48]
decw %ax
// CHECK: decl %eax # encoding: [0x48]
decl %eax
fix a regression introduced in r115243, in which the instruction backing int_x86_ssse3_pshuf_w got removed. This caused PR8280. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115422 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-02 21:32:15 +00:00
// CHECK: pshufw $14, %mm4, %mm0 # encoding: [0x0f,0x70,0xc4,0x0e]
pshufw $14, %mm4, %mm0
the immediate field of pshufw is actually an 8-bit field, not a 8-bit field that is sign extended. This fixes PR8288 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115473 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-03 19:09:13 +00:00
// CHECK: pshufw $90, %mm4, %mm0 # encoding: [0x0f,0x70,0xc4,0x5a]
// PR8288
pshufw $90, %mm4, %mm0
Added a handful of x86-32 instructions that were missing so that llvm-mc would be more complete. These are only expected to be used by llvm-mc with assembly source so there is no pattern, [], in the .td files. Most are being added to X86InstrInfo.td as Chris suggested and only comments about register uses are added. Suggestions welcome on the .td changes as I'm not sure on every detail of the x86 records. More missing instructions will be coming. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116716 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-18 17:04:36 +00:00
// rdar://8416805
// CHECK: aaa
// CHECK: encoding: [0x37]
aaa
// CHECK: aad $1
// CHECK: encoding: [0xd5,0x01]
aad $1
Have the X86 back-end emit the alias instead of what's being aliased. In most cases, it's much nicer and more informative reading the alias. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129497 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-14 01:11:51 +00:00
// CHECK: aad
Added a handful of x86-32 instructions that were missing so that llvm-mc would be more complete. These are only expected to be used by llvm-mc with assembly source so there is no pattern, [], in the .td files. Most are being added to X86InstrInfo.td as Chris suggested and only comments about register uses are added. Suggestions welcome on the .td changes as I'm not sure on every detail of the x86 records. More missing instructions will be coming. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116716 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-18 17:04:36 +00:00
// CHECK: encoding: [0xd5,0x0a]
aad $0xA
Have the X86 back-end emit the alias instead of what's being aliased. In most cases, it's much nicer and more informative reading the alias. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129497 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-14 01:11:51 +00:00
// CHECK: aad
Added a handful of x86-32 instructions that were missing so that llvm-mc would be more complete. These are only expected to be used by llvm-mc with assembly source so there is no pattern, [], in the .td files. Most are being added to X86InstrInfo.td as Chris suggested and only comments about register uses are added. Suggestions welcome on the .td changes as I'm not sure on every detail of the x86 records. More missing instructions will be coming. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116716 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-18 17:04:36 +00:00
// CHECK: encoding: [0xd5,0x0a]
aad
// CHECK: aam $2
// CHECK: encoding: [0xd4,0x02]
aam $2
Have the X86 back-end emit the alias instead of what's being aliased. In most cases, it's much nicer and more informative reading the alias. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129497 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-14 01:11:51 +00:00
// CHECK: aam
Added a handful of x86-32 instructions that were missing so that llvm-mc would be more complete. These are only expected to be used by llvm-mc with assembly source so there is no pattern, [], in the .td files. Most are being added to X86InstrInfo.td as Chris suggested and only comments about register uses are added. Suggestions welcome on the .td changes as I'm not sure on every detail of the x86 records. More missing instructions will be coming. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116716 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-18 17:04:36 +00:00
// CHECK: encoding: [0xd4,0x0a]
aam $0xA
Have the X86 back-end emit the alias instead of what's being aliased. In most cases, it's much nicer and more informative reading the alias. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129497 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-14 01:11:51 +00:00
// CHECK: aam
Added a handful of x86-32 instructions that were missing so that llvm-mc would be more complete. These are only expected to be used by llvm-mc with assembly source so there is no pattern, [], in the .td files. Most are being added to X86InstrInfo.td as Chris suggested and only comments about register uses are added. Suggestions welcome on the .td changes as I'm not sure on every detail of the x86 records. More missing instructions will be coming. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116716 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-18 17:04:36 +00:00
// CHECK: encoding: [0xd4,0x0a]
aam
// CHECK: aas
// CHECK: encoding: [0x3f]
aas
// CHECK: daa
// CHECK: encoding: [0x27]
daa
// CHECK: das
// CHECK: encoding: [0x2f]
das
// CHECK: retw $31438
// CHECK: encoding: [0x66,0xc2,0xce,0x7a]
retw $0x7ace
// CHECK: lretw $31438
// CHECK: encoding: [0x66,0xca,0xce,0x7a]
lretw $0x7ace
// CHECK: bound 2(%eax), %bx
// CHECK: encoding: [0x66,0x62,0x58,0x02]
bound 2(%eax),%bx
// CHECK: bound 4(%ebx), %ecx
// CHECK: encoding: [0x62,0x4b,0x04]
bound 4(%ebx),%ecx
// CHECK: arpl %bx, %bx
// CHECK: encoding: [0x63,0xdb]
arpl %bx,%bx
// CHECK: arpl %bx, 6(%ecx)
// CHECK: encoding: [0x63,0x59,0x06]
arpl %bx,6(%ecx)
Added a few tweaks to the Intel Descriptor-table support instructions to allow word forms and suffixed versions to match the darwin assembler in 32-bit and 64-bit modes. This is again for use just with assembly source for llvm-mc . git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116773 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-19 00:01:44 +00:00
// CHECK: lgdtw 4(%eax)
// CHECK: encoding: [0x66,0x0f,0x01,0x50,0x04]
lgdtw 4(%eax)
[x86] Disambiguate [LS][IG]DT{32,64}m and add 16-bit versions, fix aliases git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198755 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-08 12:57:55 +00:00
// CHECK: lgdtl 4(%eax)
Added a few tweaks to the Intel Descriptor-table support instructions to allow word forms and suffixed versions to match the darwin assembler in 32-bit and 64-bit modes. This is again for use just with assembly source for llvm-mc . git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116773 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-19 00:01:44 +00:00
// CHECK: encoding: [0x0f,0x01,0x50,0x04]
lgdt 4(%eax)
[x86] Disambiguate [LS][IG]DT{32,64}m and add 16-bit versions, fix aliases git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198755 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-08 12:57:55 +00:00
// CHECK: lgdtl 4(%eax)
Added a few tweaks to the Intel Descriptor-table support instructions to allow word forms and suffixed versions to match the darwin assembler in 32-bit and 64-bit modes. This is again for use just with assembly source for llvm-mc . git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116773 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-19 00:01:44 +00:00
// CHECK: encoding: [0x0f,0x01,0x50,0x04]
lgdtl 4(%eax)
// CHECK: lidtw 4(%eax)
// CHECK: encoding: [0x66,0x0f,0x01,0x58,0x04]
lidtw 4(%eax)
[x86] Disambiguate [LS][IG]DT{32,64}m and add 16-bit versions, fix aliases git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198755 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-08 12:57:55 +00:00
// CHECK: lidtl 4(%eax)
Added a few tweaks to the Intel Descriptor-table support instructions to allow word forms and suffixed versions to match the darwin assembler in 32-bit and 64-bit modes. This is again for use just with assembly source for llvm-mc . git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116773 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-19 00:01:44 +00:00
// CHECK: encoding: [0x0f,0x01,0x58,0x04]
lidt 4(%eax)
[x86] Disambiguate [LS][IG]DT{32,64}m and add 16-bit versions, fix aliases git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198755 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-08 12:57:55 +00:00
// CHECK: lidtl 4(%eax)
Added a few tweaks to the Intel Descriptor-table support instructions to allow word forms and suffixed versions to match the darwin assembler in 32-bit and 64-bit modes. This is again for use just with assembly source for llvm-mc . git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116773 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-19 00:01:44 +00:00
// CHECK: encoding: [0x0f,0x01,0x58,0x04]
lidtl 4(%eax)
// CHECK: sgdtw 4(%eax)
// CHECK: encoding: [0x66,0x0f,0x01,0x40,0x04]
sgdtw 4(%eax)
[x86] Disambiguate [LS][IG]DT{32,64}m and add 16-bit versions, fix aliases git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198755 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-08 12:57:55 +00:00
// CHECK: sgdtl 4(%eax)
Added a few tweaks to the Intel Descriptor-table support instructions to allow word forms and suffixed versions to match the darwin assembler in 32-bit and 64-bit modes. This is again for use just with assembly source for llvm-mc . git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116773 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-19 00:01:44 +00:00
// CHECK: encoding: [0x0f,0x01,0x40,0x04]
sgdt 4(%eax)
[x86] Disambiguate [LS][IG]DT{32,64}m and add 16-bit versions, fix aliases git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198755 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-08 12:57:55 +00:00
// CHECK: sgdtl 4(%eax)
Added a few tweaks to the Intel Descriptor-table support instructions to allow word forms and suffixed versions to match the darwin assembler in 32-bit and 64-bit modes. This is again for use just with assembly source for llvm-mc . git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116773 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-19 00:01:44 +00:00
// CHECK: encoding: [0x0f,0x01,0x40,0x04]
sgdtl 4(%eax)
// CHECK: sidtw 4(%eax)
// CHECK: encoding: [0x66,0x0f,0x01,0x48,0x04]
sidtw 4(%eax)
[x86] Disambiguate [LS][IG]DT{32,64}m and add 16-bit versions, fix aliases git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198755 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-08 12:57:55 +00:00
// CHECK: sidtl 4(%eax)
Added a few tweaks to the Intel Descriptor-table support instructions to allow word forms and suffixed versions to match the darwin assembler in 32-bit and 64-bit modes. This is again for use just with assembly source for llvm-mc . git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116773 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-19 00:01:44 +00:00
// CHECK: encoding: [0x0f,0x01,0x48,0x04]
sidt 4(%eax)
[x86] Disambiguate [LS][IG]DT{32,64}m and add 16-bit versions, fix aliases git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198755 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-08 12:57:55 +00:00
// CHECK: sidtl 4(%eax)
Added a few tweaks to the Intel Descriptor-table support instructions to allow word forms and suffixed versions to match the darwin assembler in 32-bit and 64-bit modes. This is again for use just with assembly source for llvm-mc . git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116773 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-19 00:01:44 +00:00
// CHECK: encoding: [0x0f,0x01,0x48,0x04]
sidtl 4(%eax)
Added some aliases to the fcomip and fucompi Intel instructions. So that llvm-mc will accept versions that the darwin assembler allows. Forms ending in "pi" and forms without all the operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117427 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27 00:59:28 +00:00
go to great lengths to work around a GAS bug my previous patch exposed: GAS doesn't accept "fcomip %st(1)", it requires "fcomip %st(1), %st(0)" even though st(0) is implicit in all other fp stack instructions. Fortunately, there is an alias for fcomip named "fcompi" and gas does accept the default argument for the alias (boggle!). As such, switch the canonical form of this instruction to "pi" instead of "ip". This makes the code generator and disassembler generate pi, avoiding the gas bug. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118356 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 21:37:06 +00:00
// CHECK: fcompi %st(2)
Added some aliases to the fcomip and fucompi Intel instructions. So that llvm-mc will accept versions that the darwin assembler allows. Forms ending in "pi" and forms without all the operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117427 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27 00:59:28 +00:00
// CHECK: encoding: [0xdf,0xf2]
go to great lengths to work around a GAS bug my previous patch exposed: GAS doesn't accept "fcomip %st(1)", it requires "fcomip %st(1), %st(0)" even though st(0) is implicit in all other fp stack instructions. Fortunately, there is an alias for fcomip named "fcompi" and gas does accept the default argument for the alias (boggle!). As such, switch the canonical form of this instruction to "pi" instead of "ip". This makes the code generator and disassembler generate pi, avoiding the gas bug. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118356 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 21:37:06 +00:00
fcompi %st(2), %st
Added some aliases to the fcomip and fucompi Intel instructions. So that llvm-mc will accept versions that the darwin assembler allows. Forms ending in "pi" and forms without all the operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117427 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27 00:59:28 +00:00
go to great lengths to work around a GAS bug my previous patch exposed: GAS doesn't accept "fcomip %st(1)", it requires "fcomip %st(1), %st(0)" even though st(0) is implicit in all other fp stack instructions. Fortunately, there is an alias for fcomip named "fcompi" and gas does accept the default argument for the alias (boggle!). As such, switch the canonical form of this instruction to "pi" instead of "ip". This makes the code generator and disassembler generate pi, avoiding the gas bug. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118356 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 21:37:06 +00:00
// CHECK: fcompi %st(2)
Added some aliases to the fcomip and fucompi Intel instructions. So that llvm-mc will accept versions that the darwin assembler allows. Forms ending in "pi" and forms without all the operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117427 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27 00:59:28 +00:00
// CHECK: encoding: [0xdf,0xf2]
fcompi %st(2)
Have the X86 back-end emit the alias instead of what's being aliased. In most cases, it's much nicer and more informative reading the alias. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129497 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-14 01:11:51 +00:00
// CHECK: fcompi
Added some aliases to the fcomip and fucompi Intel instructions. So that llvm-mc will accept versions that the darwin assembler allows. Forms ending in "pi" and forms without all the operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117427 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27 00:59:28 +00:00
// CHECK: encoding: [0xdf,0xf1]
fcompi
go to great lengths to work around a GAS bug my previous patch exposed: GAS doesn't accept "fcomip %st(1)", it requires "fcomip %st(1), %st(0)" even though st(0) is implicit in all other fp stack instructions. Fortunately, there is an alias for fcomip named "fcompi" and gas does accept the default argument for the alias (boggle!). As such, switch the canonical form of this instruction to "pi" instead of "ip". This makes the code generator and disassembler generate pi, avoiding the gas bug. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118356 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 21:37:06 +00:00
// CHECK: fucompi %st(2)
Added some aliases to the fcomip and fucompi Intel instructions. So that llvm-mc will accept versions that the darwin assembler allows. Forms ending in "pi" and forms without all the operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117427 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27 00:59:28 +00:00
// CHECK: encoding: [0xdf,0xea]
fucompi %st(2),%st
go to great lengths to work around a GAS bug my previous patch exposed: GAS doesn't accept "fcomip %st(1)", it requires "fcomip %st(1), %st(0)" even though st(0) is implicit in all other fp stack instructions. Fortunately, there is an alias for fcomip named "fcompi" and gas does accept the default argument for the alias (boggle!). As such, switch the canonical form of this instruction to "pi" instead of "ip". This makes the code generator and disassembler generate pi, avoiding the gas bug. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118356 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-06 21:37:06 +00:00
// CHECK: fucompi %st(2)
Added some aliases to the fcomip and fucompi Intel instructions. So that llvm-mc will accept versions that the darwin assembler allows. Forms ending in "pi" and forms without all the operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117427 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27 00:59:28 +00:00
// CHECK: encoding: [0xdf,0xea]
fucompi %st(2)
Have the X86 back-end emit the alias instead of what's being aliased. In most cases, it's much nicer and more informative reading the alias. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129497 91177308-0d34-0410-b5e6-96231b3b80d8
2011-04-14 01:11:51 +00:00
// CHECK: fucompi
Added some aliases to the fcomip and fucompi Intel instructions. So that llvm-mc will accept versions that the darwin assembler allows. Forms ending in "pi" and forms without all the operands. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117427 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27 00:59:28 +00:00
// CHECK: encoding: [0xdf,0xe9]
fucompi
Tweaks to X86 instructions to allow the 'w' suffix in places it makes sense, when the instruction takes the 16-bit ax register or m16 memory location. These changes to llvm-mc matches what the darwin assembler allows for these instructions. Done differently than in r117031 that caused a valgrind error which was later reverted. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117433 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27 02:32:19 +00:00
// CHECK: fldcw 32493
// CHECK: encoding: [0xd9,0x2d,0xed,0x7e,0x00,0x00]
fldcww 0x7eed
// CHECK: fldcw 32493
// CHECK: encoding: [0xd9,0x2d,0xed,0x7e,0x00,0x00]
fldcw 0x7eed
// CHECK: fnstcw 32493
// CHECK: encoding: [0xd9,0x3d,0xed,0x7e,0x00,0x00]
fnstcww 0x7eed
// CHECK: fnstcw 32493
// CHECK: encoding: [0xd9,0x3d,0xed,0x7e,0x00,0x00]
fnstcw 0x7eed
// CHECK: wait
// CHECK: encoding: [0x9b]
fstcww 0x7eed
// CHECK: wait
// CHECK: encoding: [0x9b]
fstcw 0x7eed
// CHECK: fnstsw 32493
// CHECK: encoding: [0xdd,0x3d,0xed,0x7e,0x00,0x00]
fnstsww 0x7eed
// CHECK: fnstsw 32493
// CHECK: encoding: [0xdd,0x3d,0xed,0x7e,0x00,0x00]
fnstsw 0x7eed
// CHECK: wait
// CHECK: encoding: [0x9b]
fstsww 0x7eed
// CHECK: wait
// CHECK: encoding: [0x9b]
fstsw 0x7eed
// CHECK: verr 32493
// CHECK: encoding: [0x0f,0x00,0x25,0xed,0x7e,0x00,0x00]
verrw 0x7eed
// CHECK: verr 32493
// CHECK: encoding: [0x0f,0x00,0x25,0xed,0x7e,0x00,0x00]
verr 0x7eed
Another tweak to X86 instructions to add the missing flex instruction (without the wait prefix). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117434 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27 02:53:04 +00:00
// CHECK: wait
// CHECK: encoding: [0x9b]
fclex
// CHECK: fnclex
// CHECK: encoding: [0xdb,0xe2]
fnclex
Yet another tweak to X86 instructions to add ud2a as an alias to ud2 (still to add ud2b). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117435 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27 03:01:02 +00:00
add a test for the ud2a alias. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117803 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-30 17:01:25 +00:00
// CHECK: ud2
// CHECK: encoding: [0x0f,0x0b]
ud2
Yet another tweak to X86 instructions to add ud2a as an alias to ud2 (still to add ud2b). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117435 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27 03:01:02 +00:00
// CHECK: ud2
// CHECK: encoding: [0x0f,0x0b]
ud2a
Added the x86 instruction ud2b (2nd official undefined instruction). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117485 91177308-0d34-0410-b5e6-96231b3b80d8
2010-10-27 20:46:49 +00:00
// CHECK: ud2b
// CHECK: encoding: [0x0f,0xb9]
ud2b
Recognize loopz and loopnz as aliases for loope and loopne. From Dimitry Andric. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126168 91177308-0d34-0410-b5e6-96231b3b80d8
2011-02-22 00:43:07 +00:00
// CHECK: loope 0
// CHECK: encoding: [0xe1,A]
loopz 0
// CHECK: loopne 0
// CHECK: encoding: [0xe0,A]
loopnz 0
PR9377: Handle x86 str with register operand in a way consistent with gas. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126970 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-04 00:10:17 +00:00
Support explicit argument forms for the X86 string instructions. For now, only the default segments are supported. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127875 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-18 11:59:40 +00:00
// CHECK: outsb # encoding: [0x6e]
// CHECK: outsb
// CHECK: outsb
outsb
outsb %ds:(%esi), %dx
outsb (%esi), %dx
// CHECK: outsw # encoding: [0x66,0x6f]
// CHECK: outsw
// CHECK: outsw
outsw
outsw %ds:(%esi), %dx
outsw (%esi), %dx
// CHECK: outsl # encoding: [0x6f]
// CHECK: outsl
outsl
outsl %ds:(%esi), %dx
outsl (%esi), %dx
// CHECK: insb # encoding: [0x6c]
// CHECK: insb
insb
insb %dx, %es:(%edi)
// CHECK: insw # encoding: [0x66,0x6d]
// CHECK: insw
insw
insw %dx, %es:(%edi)
// CHECK: insl # encoding: [0x6d]
// CHECK: insl
insl
insl %dx, %es:(%edi)
// CHECK: movsb # encoding: [0xa4]
// CHECK: movsb
// CHECK: movsb
movsb
movsb %ds:(%esi), %es:(%edi)
movsb (%esi), %es:(%edi)
// CHECK: movsw # encoding: [0x66,0xa5]
// CHECK: movsw
// CHECK: movsw
movsw
movsw %ds:(%esi), %es:(%edi)
movsw (%esi), %es:(%edi)
Don't let x86 asm printer use the no operand movsd alias. It should use the normal movsl instead. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186924 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-23 01:50:47 +00:00
// CHECK: movsl # encoding: [0xa5]
// CHECK: movsl
// CHECK: movsl
Support explicit argument forms for the X86 string instructions. For now, only the default segments are supported. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127875 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-18 11:59:40 +00:00
movsl
movsl %ds:(%esi), %es:(%edi)
movsl (%esi), %es:(%edi)
// CHECK: lodsb # encoding: [0xac]
// CHECK: lodsb
// CHECK: lodsb
// CHECK: lodsb
// CHECK: lodsb
lodsb
lodsb %ds:(%esi), %al
lodsb (%esi), %al
lods %ds:(%esi), %al
lods (%esi), %al
// CHECK: lodsw # encoding: [0x66,0xad]
// CHECK: lodsw
// CHECK: lodsw
// CHECK: lodsw
// CHECK: lodsw
lodsw
lodsw %ds:(%esi), %ax
lodsw (%esi), %ax
lods %ds:(%esi), %ax
lods (%esi), %ax
// CHECK: lodsl # encoding: [0xad]
// CHECK: lodsl
// CHECK: lodsl
// CHECK: lodsl
// CHECK: lodsl
lodsl
lodsl %ds:(%esi), %eax
lodsl (%esi), %eax
lods %ds:(%esi), %eax
lods (%esi), %eax
// CHECK: stosb # encoding: [0xaa]
// CHECK: stosb
// CHECK: stosb
stosb
stosb %al, %es:(%edi)
stos %al, %es:(%edi)
// CHECK: stosw # encoding: [0x66,0xab]
// CHECK: stosw
// CHECK: stosw
stosw
stosw %ax, %es:(%edi)
stos %ax, %es:(%edi)
// CHECK: stosl # encoding: [0xab]
// CHECK: stosl
// CHECK: stosl
stosl
stosl %eax, %es:(%edi)
stos %eax, %es:(%edi)
PR9377: Handle x86 str with register operand in a way consistent with gas. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126970 91177308-0d34-0410-b5e6-96231b3b80d8
2011-03-04 00:10:17 +00:00
// CHECK: strw
// CHECK: encoding: [0x66,0x0f,0x00,0xc8]
str %ax
// CHECK: strl
// CHECK: encoding: [0x0f,0x00,0xc8]
str %eax
testcase for PR9378 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131875 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-22 22:32:53 +00:00
// PR9378
// CHECK: fsubp
// CHECK: encoding: [0xde,0xe1]
fsubp %st,%st(1)
add test from PR9164 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131876 91177308-0d34-0410-b5e6-96231b3b80d8
2011-05-22 22:35:34 +00:00
// PR9164
// CHECK: fsubp %st(2)
// CHECK: encoding: [0xde,0xe2]
fsubp %st, %st(2)
Fix assembling of xchg %eax, %eax to not use the NOP encoding of 0x90. This was done by creating a new register group that excludes AX registers. Fixes PR10345. Also added aliases for flipping the order of the operands of xchg <reg>, %eax. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141274 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-06 06:44:41 +00:00
// PR10345
// CHECK: xchgl %eax, %eax
Revert part of r141274. Only need to change encoding for xchg %eax, %eax in 64-bit mode. This is because in 64-bit mode xchg %eax, %eax implies zeroing the upper 32-bits of RAX which makes it not a NOP. In 32-bit mode using NOP encoding is fine. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141353 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07 05:35:38 +00:00
// CHECK: encoding: [0x90]
Fix assembling of xchg %eax, %eax to not use the NOP encoding of 0x90. This was done by creating a new register group that excludes AX registers. Fixes PR10345. Also added aliases for flipping the order of the operands of xchg <reg>, %eax. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141274 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-06 06:44:41 +00:00
xchgl %eax, %eax
// CHECK: xchgw %ax, %ax
Revert part of r141274. Only need to change encoding for xchg %eax, %eax in 64-bit mode. This is because in 64-bit mode xchg %eax, %eax implies zeroing the upper 32-bits of RAX which makes it not a NOP. In 32-bit mode using NOP encoding is fine. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141353 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-07 05:35:38 +00:00
// CHECK: encoding: [0x66,0x90]
Fix assembling of xchg %eax, %eax to not use the NOP encoding of 0x90. This was done by creating a new register group that excludes AX registers. Fixes PR10345. Also added aliases for flipping the order of the operands of xchg <reg>, %eax. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141274 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-06 06:44:41 +00:00
xchgw %ax, %ax
// CHECK: xchgl %ecx, %eax
// CHECK: encoding: [0x91]
xchgl %ecx, %eax
// CHECK: xchgl %ecx, %eax
// CHECK: encoding: [0x91]
xchgl %eax, %ecx
Add retw and lretw instructions. Also, fix Intel syntax parsing for all ret instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154468 91177308-0d34-0410-b5e6-96231b3b80d8
2012-04-11 01:10:53 +00:00
// CHECK: retw
// CHECK: encoding: [0x66,0xc3]
retw
// CHECK: lretw
// CHECK: encoding: [0x66,0xcb]
lretw
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