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llvm-6502/test/MC/ARM/thumb2-mclass.s

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Check in a patch that has already been code reviewed by Owen that I'd forgotten to commit. Build on previous patches to successfully distinguish between an M-series and A/R-series MSR and MRS instruction. These take different mask names and have a *slightly* different opcode format. Add decoder and disassembler tests. Improvement on the previous patch - successfully distinguish between valid v6m and v7m masks (one is a subset of the other). The patch had to be edited slightly to apply to ToT. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140696 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-28 14:21:38 +00:00
@ RUN: llvm-mc -triple=thumbv7m-apple-darwin -show-encoding < %s | FileCheck %s
Amending test/MC/ARM/thumb2-mclass.s to match its apparent original purpose (to test the ARMv6M/ARMv7M commonality), and creating a new test case for the differences between ARMv6M and ARMv7M git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198946 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-10 16:49:49 +00:00
@ RUN: llvm-mc -triple=thumbv6m -show-encoding < %s | FileCheck %s
Check in a patch that has already been code reviewed by Owen that I'd forgotten to commit. Build on previous patches to successfully distinguish between an M-series and A/R-series MSR and MRS instruction. These take different mask names and have a *slightly* different opcode format. Add decoder and disassembler tests. Improvement on the previous patch - successfully distinguish between valid v6m and v7m masks (one is a subset of the other). The patch had to be edited slightly to apply to ToT. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140696 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-28 14:21:38 +00:00
.syntax unified
.globl _func
@ Check that the assembler can handle the documented syntax from the ARM ARM.
Amending test/MC/ARM/thumb2-mclass.s to match its apparent original purpose (to test the ARMv6M/ARMv7M commonality), and creating a new test case for the differences between ARMv6M and ARMv7M git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198946 91177308-0d34-0410-b5e6-96231b3b80d8
2014-01-10 16:49:49 +00:00
@ These tests test instruction encodings specific to v6m & v7m (FeatureMClass).
Check in a patch that has already been code reviewed by Owen that I'd forgotten to commit. Build on previous patches to successfully distinguish between an M-series and A/R-series MSR and MRS instruction. These take different mask names and have a *slightly* different opcode format. Add decoder and disassembler tests. Improvement on the previous patch - successfully distinguish between valid v6m and v7m masks (one is a subset of the other). The patch had to be edited slightly to apply to ToT. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140696 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-28 14:21:38 +00:00
@------------------------------------------------------------------------------
@ MRS
@------------------------------------------------------------------------------
mrs r0, apsr
mrs r0, iapsr
mrs r0, eapsr
mrs r0, xpsr
mrs r0, ipsr
mrs r0, epsr
mrs r0, iepsr
mrs r0, msp
mrs r0, psp
mrs r0, primask
mrs r0, control
@ CHECK: mrs r0, apsr @ encoding: [0xef,0xf3,0x00,0x80]
@ CHECK: mrs r0, iapsr @ encoding: [0xef,0xf3,0x01,0x80]
@ CHECK: mrs r0, eapsr @ encoding: [0xef,0xf3,0x02,0x80]
@ CHECK: mrs r0, xpsr @ encoding: [0xef,0xf3,0x03,0x80]
@ CHECK: mrs r0, ipsr @ encoding: [0xef,0xf3,0x05,0x80]
@ CHECK: mrs r0, epsr @ encoding: [0xef,0xf3,0x06,0x80]
@ CHECK: mrs r0, iepsr @ encoding: [0xef,0xf3,0x07,0x80]
@ CHECK: mrs r0, msp @ encoding: [0xef,0xf3,0x08,0x80]
@ CHECK: mrs r0, psp @ encoding: [0xef,0xf3,0x09,0x80]
@ CHECK: mrs r0, primask @ encoding: [0xef,0xf3,0x10,0x80]
@ CHECK: mrs r0, control @ encoding: [0xef,0xf3,0x14,0x80]
@------------------------------------------------------------------------------
@ MSR
@------------------------------------------------------------------------------
msr apsr, r0
Fix the encoding of the armv7m (MClass) for MSR APSR writes which was missing the 0b10 mask encoding bits. Make MSR APSR writes without a _<bits> qualifier an alias for MSR APSR_nzcvq even though ARM as deprecated it use. Also add support for suffixes (_nzcvq, _g, _nzcvqg) for APSR versions. Some FIXMEs in the code for better error checking when versions shouldn't be used. rdar://11457025 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157019 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-17 22:18:01 +00:00
msr apsr_nzcvq, r0
msr apsr_g, r0
msr apsr_nzcvqg, r0
Check in a patch that has already been code reviewed by Owen that I'd forgotten to commit. Build on previous patches to successfully distinguish between an M-series and A/R-series MSR and MRS instruction. These take different mask names and have a *slightly* different opcode format. Add decoder and disassembler tests. Improvement on the previous patch - successfully distinguish between valid v6m and v7m masks (one is a subset of the other). The patch had to be edited slightly to apply to ToT. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140696 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-28 14:21:38 +00:00
msr iapsr, r0
Fix the encoding of the armv7m (MClass) for MSR APSR writes which was missing the 0b10 mask encoding bits. Make MSR APSR writes without a _<bits> qualifier an alias for MSR APSR_nzcvq even though ARM as deprecated it use. Also add support for suffixes (_nzcvq, _g, _nzcvqg) for APSR versions. Some FIXMEs in the code for better error checking when versions shouldn't be used. rdar://11457025 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157019 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-17 22:18:01 +00:00
msr iapsr_nzcvq, r0
msr iapsr_g, r0
msr iapsr_nzcvqg, r0
Check in a patch that has already been code reviewed by Owen that I'd forgotten to commit. Build on previous patches to successfully distinguish between an M-series and A/R-series MSR and MRS instruction. These take different mask names and have a *slightly* different opcode format. Add decoder and disassembler tests. Improvement on the previous patch - successfully distinguish between valid v6m and v7m masks (one is a subset of the other). The patch had to be edited slightly to apply to ToT. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140696 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-28 14:21:38 +00:00
msr eapsr, r0
Fix the encoding of the armv7m (MClass) for MSR APSR writes which was missing the 0b10 mask encoding bits. Make MSR APSR writes without a _<bits> qualifier an alias for MSR APSR_nzcvq even though ARM as deprecated it use. Also add support for suffixes (_nzcvq, _g, _nzcvqg) for APSR versions. Some FIXMEs in the code for better error checking when versions shouldn't be used. rdar://11457025 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157019 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-17 22:18:01 +00:00
msr eapsr_nzcvq, r0
msr eapsr_g, r0
msr eapsr_nzcvqg, r0
Check in a patch that has already been code reviewed by Owen that I'd forgotten to commit. Build on previous patches to successfully distinguish between an M-series and A/R-series MSR and MRS instruction. These take different mask names and have a *slightly* different opcode format. Add decoder and disassembler tests. Improvement on the previous patch - successfully distinguish between valid v6m and v7m masks (one is a subset of the other). The patch had to be edited slightly to apply to ToT. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140696 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-28 14:21:38 +00:00
msr xpsr, r0
Fix the encoding of the armv7m (MClass) for MSR APSR writes which was missing the 0b10 mask encoding bits. Make MSR APSR writes without a _<bits> qualifier an alias for MSR APSR_nzcvq even though ARM as deprecated it use. Also add support for suffixes (_nzcvq, _g, _nzcvqg) for APSR versions. Some FIXMEs in the code for better error checking when versions shouldn't be used. rdar://11457025 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157019 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-17 22:18:01 +00:00
msr xpsr_nzcvq, r0
msr xpsr_g, r0
msr xpsr_nzcvqg, r0
Check in a patch that has already been code reviewed by Owen that I'd forgotten to commit. Build on previous patches to successfully distinguish between an M-series and A/R-series MSR and MRS instruction. These take different mask names and have a *slightly* different opcode format. Add decoder and disassembler tests. Improvement on the previous patch - successfully distinguish between valid v6m and v7m masks (one is a subset of the other). The patch had to be edited slightly to apply to ToT. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140696 91177308-0d34-0410-b5e6-96231b3b80d8
2011-09-28 14:21:38 +00:00
msr ipsr, r0
msr epsr, r0
msr iepsr, r0
msr msp, r0
msr psp, r0
msr primask, r0
msr control, r0
Fix the encoding of the armv7m (MClass) for MSR APSR writes which was missing the 0b10 mask encoding bits. Make MSR APSR writes without a _<bits> qualifier an alias for MSR APSR_nzcvq even though ARM as deprecated it use. Also add support for suffixes (_nzcvq, _g, _nzcvqg) for APSR versions. Some FIXMEs in the code for better error checking when versions shouldn't be used. rdar://11457025 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157019 91177308-0d34-0410-b5e6-96231b3b80d8
2012-05-17 22:18:01 +00:00
@ CHECK: msr apsr, r0 @ encoding: [0x80,0xf3,0x00,0x88]
@ CHECK: msr apsr, r0 @ encoding: [0x80,0xf3,0x00,0x88]
@ CHECK: msr apsr_g, r0 @ encoding: [0x80,0xf3,0x00,0x84]
@ CHECK: msr apsr_nzcvqg, r0 @ encoding: [0x80,0xf3,0x00,0x8c]
@ CHECK: msr iapsr, r0 @ encoding: [0x80,0xf3,0x01,0x88]
@ CHECK: msr iapsr, r0 @ encoding: [0x80,0xf3,0x01,0x88]
@ CHECK: msr iapsr_g, r0 @ encoding: [0x80,0xf3,0x01,0x84]
@ CHECK: msr iapsr_nzcvqg, r0 @ encoding: [0x80,0xf3,0x01,0x8c]
@ CHECK: msr eapsr, r0 @ encoding: [0x80,0xf3,0x02,0x88]
@ CHECK: msr eapsr, r0 @ encoding: [0x80,0xf3,0x02,0x88]
@ CHECK: msr eapsr_g, r0 @ encoding: [0x80,0xf3,0x02,0x84]
@ CHECK: msr eapsr_nzcvqg, r0 @ encoding: [0x80,0xf3,0x02,0x8c]
@ CHECK: msr xpsr, r0 @ encoding: [0x80,0xf3,0x03,0x88]
@ CHECK: msr xpsr, r0 @ encoding: [0x80,0xf3,0x03,0x88]
@ CHECK: msr xpsr_g, r0 @ encoding: [0x80,0xf3,0x03,0x84]
@ CHECK: msr xpsr_nzcvqg, r0 @ encoding: [0x80,0xf3,0x03,0x8c]
Fix the encoding of the armv7m (MClass) for MSR registers other than aspr, iaspr, espr and xpsr which also needed to have 0b10 in their mask encoding bits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158560 91177308-0d34-0410-b5e6-96231b3b80d8
2012-06-15 22:14:44 +00:00
@ CHECK: msr ipsr, r0 @ encoding: [0x80,0xf3,0x05,0x88]
@ CHECK: msr epsr, r0 @ encoding: [0x80,0xf3,0x06,0x88]
@ CHECK: msr iepsr, r0 @ encoding: [0x80,0xf3,0x07,0x88]
@ CHECK: msr msp, r0 @ encoding: [0x80,0xf3,0x08,0x88]
@ CHECK: msr psp, r0 @ encoding: [0x80,0xf3,0x09,0x88]
@ CHECK: msr primask, r0 @ encoding: [0x80,0xf3,0x10,0x88]
@ CHECK: msr control, r0 @ encoding: [0x80,0xf3,0x14,0x88]
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