llvm-6502/test/MC/Disassembler/AArch64/ldp-offset-predictable.txt

# RUN: llvm-mc -triple=aarch64 -disassemble < %s 2>&1 | FileCheck %s

# Stores are OK.
0xe0 0x83 0x00 0xa9
# CHECK-NOT: potentially undefined instruction encoding
# CHECK: stp x0, x0, [sp, #8]
Add AArch64 as an experimental target. This patch adds support for AArch64 (ARM's 64-bit architecture) to LLVM in the "experimental" category. Currently, it won't be built unless requested explicitly. This initial commit should have support for: + Assembly of all scalar (i.e. non-NEON, non-Crypto) instructions (except the late addition CRC instructions). + CodeGen features required for C++03 and C99. + Compilation for the "small" memory model: code+static data < 4GB. + Absolute and position-independent code. + GNU-style (i.e. "__thread") TLS. + Debugging information. The principal omission, currently, is performance tuning. This patch excludes the NEON support also reviewed due to an outbreak of batshit insanity in our legal department. That will be committed soon bringing the changes to precisely what has been approved. Further reviews would be gratefully received. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174054 91177308-0d34-0410-b5e6-96231b3b80d8 2013-01-31 12:12:40 +00:00			`# RUN: llvm-mc -triple=aarch64 -disassemble < %s 2>&1 \| FileCheck %s`

			`# Stores are OK.`
			`0xe0 0x83 0x00 0xa9`
			`# CHECK-NOT: potentially undefined instruction encoding`
			`# CHECK: stp x0, x0, [sp, #8]`