6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-28 19:31:58 +00:00
Code Issues Projects Releases Wiki Activity
c55accaddb
llvm-6502/test/MC/ARM/neon-vst-encoding.s

147 lines
6.8 KiB
ArmAsm
Raw Normal View History

Add correct encodings for the basic form of vst1. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118067 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-02 21:06:06 +00:00
@ RUN: llvm-mc -mcpu=cortex-a8 -triple armv7-apple-darwin -show-encoding < %s | FileCheck %s
ARM VLD1/VST1 (one register, no writeback) assembly parsing and encoding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142583 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-20 15:04:25 +00:00
vst1.8 {d16}, [r0, :64]
Enable some VST1 tests and add a few more. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145443 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-29 22:40:32 +00:00
vst1.16 {d16}, [r0]
vst1.32 {d16}, [r0]
vst1.64 {d16}, [r0]
vst1.8 {d16, d17}, [r0, :64]
vst1.16 {d16, d17}, [r0, :128]
vst1.32 {d16, d17}, [r0]
vst1.64 {d16, d17}, [r0]
vst1.8 {d16, d17, d18}, [r0, :64]
vst1.8 {d16, d17, d18}, [r0, :64]!
vst1.8 {d16, d17, d18}, [r0], r3
ARM assembly parsing and encoding for four-register VST1. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145450 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-29 22:58:48 +00:00
vst1.8 {d16, d17, d18, d19}, [r0, :64]
vst1.16 {d16, d17, d18, d19}, [r1, :64]!
vst1.64 {d16, d17, d18, d19}, [r3], r2
Add correct encodings for the basic form of vst1. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118067 91177308-0d34-0410-b5e6-96231b3b80d8
2010-11-02 21:06:06 +00:00
Tidy up formatting. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142582 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-20 14:57:47 +00:00
@ CHECK: vst1.8 {d16}, [r0, :64] @ encoding: [0x1f,0x07,0x40,0xf4]
Enable some VST1 tests and add a few more. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145443 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-29 22:40:32 +00:00
@ CHECK: vst1.16 {d16}, [r0] @ encoding: [0x4f,0x07,0x40,0xf4]
@ CHECK: vst1.32 {d16}, [r0] @ encoding: [0x8f,0x07,0x40,0xf4]
@ CHECK: vst1.64 {d16}, [r0] @ encoding: [0xcf,0x07,0x40,0xf4]
@ CHECK: vst1.8 {d16, d17}, [r0, :64] @ encoding: [0x1f,0x0a,0x40,0xf4]
@ CHECK: vst1.16 {d16, d17}, [r0, :128] @ encoding: [0x6f,0x0a,0x40,0xf4]
@ CHECK: vst1.32 {d16, d17}, [r0] @ encoding: [0x8f,0x0a,0x40,0xf4]
@ CHECK: vst1.64 {d16, d17}, [r0] @ encoding: [0xcf,0x0a,0x40,0xf4]
@ CHECK: vst1.8 {d16, d17, d18}, [r0, :64] @ encoding: [0x1f,0x06,0x40,0xf4]
@ CHECK: vst1.8 {d16, d17, d18}, [r0, :64]! @ encoding: [0x1d,0x06,0x40,0xf4]
@ CHECK: vst1.8 {d16, d17, d18}, [r0], r3 @ encoding: [0x03,0x06,0x40,0xf4]
ARM assembly parsing and encoding for four-register VST1. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145450 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-29 22:58:48 +00:00
@ CHECK: vst1.8 {d16, d17, d18, d19}, [r0, :64] @ encoding: [0x1f,0x02,0x40,0xf4]
@ CHECK: vst1.16 {d16, d17, d18, d19}, [r1, :64]! @ encoding: [0x5d,0x02,0x41,0xf4]
@ CHECK: vst1.64 {d16, d17, d18, d19}, [r3], r2 @ encoding: [0xc2,0x02,0x43,0xf4]
ARM VLD1/VST1 (one register, no writeback) assembly parsing and encoding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142583 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-20 15:04:25 +00:00
ARM NEON VST2 assembly parsing and encoding. Work in progress. Parsing for non-writeback, single spaced register lists works now. The rest have the representations better factored, but still need more to be able to parse properly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146579 91177308-0d34-0410-b5e6-96231b3b80d8
2011-12-14 19:35:22 +00:00
vst2.8 {d16, d17}, [r0, :64]
vst2.16 {d16, d17}, [r0, :128]
vst2.32 {d16, d17}, [r0]
vst2.8 {d16, d17, d18, d19}, [r0, :64]
vst2.16 {d16, d17, d18, d19}, [r0, :128]
vst2.32 {d16, d17, d18, d19}, [r0, :256]
@ CHECK: vst2.8 {d16, d17}, [r0, :64] @ encoding: [0x1f,0x08,0x40,0xf4]
@ CHECK: vst2.16 {d16, d17}, [r0, :128] @ encoding: [0x6f,0x08,0x40,0xf4]
@ CHECK: vst2.32 {d16, d17}, [r0] @ encoding: [0x8f,0x08,0x40,0xf4]
@ CHECK: vst2.8 {d16, d17, d18, d19}, [r0, :64] @ encoding: [0x1f,0x03,0x40,0xf4]
@ CHECK: vst2.16 {d16, d17, d18, d19}, [r0, :128] @ encoding: [0x6f,0x03,0x40,0xf4]
@ CHECK: vst2.32 {d16, d17, d18, d19}, [r0, :256] @ encoding: [0xbf,0x03,0x40,0xf4]
ARM VLD1/VST1 (one register, no writeback) assembly parsing and encoding. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142583 91177308-0d34-0410-b5e6-96231b3b80d8
2011-10-20 15:04:25 +00:00
@ vst3.8 {d16, d17, d18}, [r0, :64]
@ vst3.16 {d16, d17, d18}, [r0]
@ vst3.32 {d16, d17, d18}, [r0]
@ vst3.8 {d16, d18, d20}, [r0, :64]!
@ vst3.8 {d17, d19, d21}, [r0, :64]!
@ vst3.16 {d16, d18, d20}, [r0]!
@ vst3.16 {d17, d19, d21}, [r0]!
@ vst3.32 {d16, d18, d20}, [r0]!
@ vst3.32 {d17, d19, d21}, [r0]!
@ FIXME: vst3.8 {d16, d17, d18}, [r0, :64] @ encoding: [0x1f,0x04,0x40,0xf4]
@ FIXME: vst3.16 {d16, d17, d18}, [r0] @ encoding: [0x4f,0x04,0x40,0xf4]
@ FIXME: vst3.32 {d16, d17, d18}, [r0] @ encoding: [0x8f,0x04,0x40,0xf4]
@ FIXME: vst3.8 {d16, d18, d20}, [r0, :64]! @ encoding: [0x1d,0x05,0x40,0xf4]
@ FIXME: vst3.8 {d17, d19, d21}, [r0, :64]! @ encoding: [0x1d,0x15,0x40,0xf4]
@ FIXME: vst3.16 {d16, d18, d20}, [r0]! @ encoding: [0x4d,0x05,0x40,0xf4]
@ FIXME: vst3.16 {d17, d19, d21}, [r0]! @ encoding: [0x4d,0x15,0x40,0xf4]
@ FIXME: vst3.32 {d16, d18, d20}, [r0]! @ encoding: [0x8d,0x05,0x40,0xf4]
@ FIXME: vst3.32 {d17, d19, d21}, [r0]! @ encoding: [0x8d,0x15,0x40,0xf4]
@ vst4.8 {d16, d17, d18, d19}, [r0, :64]
@ vst4.16 {d16, d17, d18, d19}, [r0, :128]
@ vst4.8 {d16, d18, d20, d22}, [r0, :256]!
@ vst4.8 {d17, d19, d21, d23}, [r0, :256]!
@ vst4.16 {d16, d18, d20, d22}, [r0]!
@ vst4.16 {d17, d19, d21, d23}, [r0]!
@ vst4.32 {d16, d18, d20, d22}, [r0]!
@ vst4.32 {d17, d19, d21, d23}, [r0]!
@ FIXME: vst4.8 {d16, d17, d18, d19}, [r0, :64] @ encoding: [0x1f,0x00,0x40,0xf4]
@ FIXME: vst4.16 {d16, d17, d18, d19}, [r0, :128] @ encoding: [0x6f,0x00,0x40,0xf4]
@ FIXME: vst4.8 {d16, d18, d20, d22}, [r0, :256]! @ encoding: [0x3d,0x01,0x40,0xf4]
@ FIXME: vst4.8 {d17, d19, d21, d23}, [r0, :256]! @ encoding: [0x3d,0x11,0x40,0xf4]
@ FIXME: vst4.16 {d16, d18, d20, d22}, [r0]! @ encoding: [0x4d,0x01,0x40,0xf4]
@ FIXME: vst4.16 {d17, d19, d21, d23}, [r0]! @ encoding: [0x4d,0x11,0x40,0xf4]
@ FIXME: vst4.32 {d16, d18, d20, d22}, [r0]! @ encoding: [0x8d,0x01,0x40,0xf4]
@ FIXME: vst4.32 {d17, d19, d21, d23}, [r0]! @ encoding: [0x8d,0x11,0x40,0xf4]
@ vst2.8 {d16[1], d17[1]}, [r0, :16]
@ vst2.16 {d16[1], d17[1]}, [r0, :32]
@ vst2.32 {d16[1], d17[1]}, [r0]
@ vst2.16 {d17[1], d19[1]}, [r0]
@ vst2.32 {d17[0], d19[0]}, [r0, :64]
@ FIXME: vst2.8 {d16[1], d17[1]}, [r0, :16] @ encoding: [0x3f,0x01,0xc0,0xf4]
@ FIXME: vst2.16 {d16[1], d17[1]}, [r0, :32] @ encoding: [0x5f,0x05,0xc0,0xf4]
@ FIXME: vst2.32 {d16[1], d17[1]}, [r0] @ encoding: [0x8f,0x09,0xc0,0xf4]
@ FIXME: vst2.16 {d17[1], d19[1]}, [r0] @ encoding: [0x6f,0x15,0xc0,0xf4]
@ FIXME: vst2.32 {d17[0], d19[0]}, [r0, :64] @ encoding: [0x5f,0x19,0xc0,0xf4]
@ vst3.8 {d16[1], d17[1], d18[1]}, [r0]
@ vst3.16 {d16[1], d17[1], d18[1]}, [r0]
@ vst3.32 {d16[1], d17[1], d18[1]}, [r0]
@ vst3.16 {d17[2], d19[2], d21[2]}, [r0]
@ vst3.32 {d16[0], d18[0], d20[0]}, [r0]
@ FIXME: vst3.8 {d16[1], d17[1], d18[1]}, [r0] @ encoding: [0x2f,0x02,0xc0,0xf4]
@ FIXME: vst3.16 {d16[1], d17[1], d18[1]}, [r0]@ encoding: [0x4f,0x06,0xc0,0xf4]
@ FIXME: vst3.32 {d16[1], d17[1], d18[1]}, [r0]@ encoding: [0x8f,0x0a,0xc0,0xf4]
@ FIXME: vst3.16 {d17[2], d19[2], d21[2]}, [r0]@ encoding: [0xaf,0x16,0xc0,0xf4]
@ FIXME: vst3.32 {d16[0], d18[0], d20[0]}, [r0]@ encoding: [0x4f,0x0a,0xc0,0xf4]
@ vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0, :32]
@ vst4.16 {d16[1], d17[1], d18[1], d19[1]}, [r0]
@ vst4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0, :128]
@ vst4.16 {d17[3], d19[3], d21[3], d23[3]}, [r0, :64]
@ vst4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0]
@ FIXME: vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0, :32] @ encoding: [0x3f,0x03,0xc0,0xf4]
@ FIXME: vst4.16 {d16[1], d17[1], d18[1], d19[1]}, [r0] @ encoding: [0x4f,0x07,0xc0,0xf4]
@ FIXME: vst4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0, :128] @ encoding: [0xaf,0x0b,0xc0,0xf4]
@ FIXME: vst4.16 {d17[3], d19[3], d21[3], d23[3]}, [r0, :64] @ encoding: [0xff,0x17,0xc0,0xf4]
@ FIXME: vst4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0] @ encoding: [0x4f,0x1b,0xc0,0xf4]
ARM parsing datatype suffix variants for non-writeback VST1 instructions. rdar://10435076 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144593 91177308-0d34-0410-b5e6-96231b3b80d8
2011-11-14 23:43:46 +00:00
@ Spot-check additional size-suffix aliases.
vst1.8 {d2}, [r2]
vst1.p8 {d2}, [r2]
vst1.u8 {d2}, [r2]
vst1.8 {q2}, [r2]
vst1.p8 {q2}, [r2]
vst1.u8 {q2}, [r2]
vst1.f32 {q2}, [r2]
@ CHECK: vst1.8 {d2}, [r2] @ encoding: [0x0f,0x27,0x02,0xf4]
@ CHECK: vst1.8 {d2}, [r2] @ encoding: [0x0f,0x27,0x02,0xf4]
@ CHECK: vst1.8 {d2}, [r2] @ encoding: [0x0f,0x27,0x02,0xf4]
@ CHECK: vst1.8 {d4, d5}, [r2] @ encoding: [0x0f,0x4a,0x02,0xf4]
@ CHECK: vst1.8 {d4, d5}, [r2] @ encoding: [0x0f,0x4a,0x02,0xf4]
@ CHECK: vst1.8 {d4, d5}, [r2] @ encoding: [0x0f,0x4a,0x02,0xf4]
@ CHECK: vst1.32 {d4, d5}, [r2] @ encoding: [0x8f,0x4a,0x02,0xf4]
Reference in New Issue Copy Permalink