2013-05-03 19:52:35 +00:00
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# RUN: llvm-mc -triple powerpc64-unknown-unknown --show-encoding %s | FileCheck %s
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2013-05-08 17:51:44 +00:00
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# RUN: llvm-mc -triple powerpc64-unknown-unknown -filetype=obj %s | \
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# RUN: llvm-readobj -r | FileCheck %s -check-prefix=REL
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2013-05-03 19:52:35 +00:00
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# FIXME: .TOC.@tocbase
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# CHECK: li 3, target@l # encoding: [0x38,0x60,A,A]
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2013-05-17 12:37:21 +00:00
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# CHECK-NEXT: # fixup A - offset: 2, value: target@l, kind: fixup_ppc_half16
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2013-05-15 15:07:06 +00:00
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# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_LO target 0x0
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2013-05-03 19:52:35 +00:00
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li 3, target@l
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# CHECK: addis 3, 3, target@ha # encoding: [0x3c,0x63,A,A]
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2013-05-17 12:37:21 +00:00
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# CHECK-NEXT: # fixup A - offset: 2, value: target@ha, kind: fixup_ppc_half16
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2013-05-15 15:07:06 +00:00
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# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_HA target 0x0
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2013-05-03 19:52:35 +00:00
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addis 3, 3, target@ha
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# CHECK: lis 3, target@ha # encoding: [0x3c,0x60,A,A]
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2013-05-17 12:37:21 +00:00
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# CHECK-NEXT: # fixup A - offset: 2, value: target@ha, kind: fixup_ppc_half16
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2013-05-15 15:07:06 +00:00
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# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_HA target 0x0
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2013-05-03 19:52:35 +00:00
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lis 3, target@ha
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# CHECK: addi 4, 3, target@l # encoding: [0x38,0x83,A,A]
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2013-05-17 12:37:21 +00:00
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# CHECK-NEXT: # fixup A - offset: 2, value: target@l, kind: fixup_ppc_half16
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2013-05-15 15:07:06 +00:00
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# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_LO target 0x0
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2013-05-03 19:52:35 +00:00
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addi 4, 3, target@l
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[PowerPC] Fix processing of ha16/lo16 fixups
The current PowerPC MC back end distinguishes between fixup_ppc_ha16
and fixup_ppc_lo16, which are determined by the instruction the fixup
applies to, and uses this distinction to decide whether a fixup ought
to resolve to the high or the low part of a symbol address.
This isn't quite correct, however. It is valid -if unusual- assembler
to use, e.g.
li 1, symbol@ha
or
lis 1, symbol@l
Whether the high or the low part of the address is used depends solely
on the @ suffix, not on the instruction.
In addition, both
li 1, symbol
and
lis 1, symbol
are valid, assuming the symbol address fits into 16 bits; again, both
will then refer to the actual symbol value (so li will load the value
itself, while lis will load the value shifted by 16).
To fix this, two places need to be adapted. If the fixup cannot be
resolved at assembler time, a relocation needs to be emitted via
PPCELFObjectWriter::getRelocType. This routine already looks at
the VK_ type to determine the relocation. The only problem is that
will reject any _LO modifier in a ha16 fixup and vice versa. This
is simply incorrect; any of those modifiers ought to be accepted
for either fixup type.
If the fixup *can* be resolved at assembler time, adjustFixupValue
currently selects the high bits of the symbol value if the fixup
type is ha16. Again, this is incorrect; see the above example
lis 1, symbol
Now, in theory we'd have to respect a VK_ modifier here. However,
in fact common code never even attempts to resolve symbol references
using any nontrivial VK_ modifier at assembler time; it will always
fall back to emitting a reloc and letting the linker handle it.
If this ever changes, presumably there'd have to be a target callback
to resolve VK_ modifiers. We'd then have to handle @ha etc. there.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182091 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-17 12:36:29 +00:00
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# CHECK: li 3, target@ha # encoding: [0x38,0x60,A,A]
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2013-05-17 12:37:21 +00:00
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# CHECK-NEXT: # fixup A - offset: 2, value: target@ha, kind: fixup_ppc_half16
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[PowerPC] Fix processing of ha16/lo16 fixups
The current PowerPC MC back end distinguishes between fixup_ppc_ha16
and fixup_ppc_lo16, which are determined by the instruction the fixup
applies to, and uses this distinction to decide whether a fixup ought
to resolve to the high or the low part of a symbol address.
This isn't quite correct, however. It is valid -if unusual- assembler
to use, e.g.
li 1, symbol@ha
or
lis 1, symbol@l
Whether the high or the low part of the address is used depends solely
on the @ suffix, not on the instruction.
In addition, both
li 1, symbol
and
lis 1, symbol
are valid, assuming the symbol address fits into 16 bits; again, both
will then refer to the actual symbol value (so li will load the value
itself, while lis will load the value shifted by 16).
To fix this, two places need to be adapted. If the fixup cannot be
resolved at assembler time, a relocation needs to be emitted via
PPCELFObjectWriter::getRelocType. This routine already looks at
the VK_ type to determine the relocation. The only problem is that
will reject any _LO modifier in a ha16 fixup and vice versa. This
is simply incorrect; any of those modifiers ought to be accepted
for either fixup type.
If the fixup *can* be resolved at assembler time, adjustFixupValue
currently selects the high bits of the symbol value if the fixup
type is ha16. Again, this is incorrect; see the above example
lis 1, symbol
Now, in theory we'd have to respect a VK_ modifier here. However,
in fact common code never even attempts to resolve symbol references
using any nontrivial VK_ modifier at assembler time; it will always
fall back to emitting a reloc and letting the linker handle it.
If this ever changes, presumably there'd have to be a target callback
to resolve VK_ modifiers. We'd then have to handle @ha etc. there.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182091 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-17 12:36:29 +00:00
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# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_HA target 0x0
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li 3, target@ha
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# CHECK: lis 3, target@l # encoding: [0x3c,0x60,A,A]
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2013-05-17 12:37:21 +00:00
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# CHECK-NEXT: # fixup A - offset: 2, value: target@l, kind: fixup_ppc_half16
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[PowerPC] Fix processing of ha16/lo16 fixups
The current PowerPC MC back end distinguishes between fixup_ppc_ha16
and fixup_ppc_lo16, which are determined by the instruction the fixup
applies to, and uses this distinction to decide whether a fixup ought
to resolve to the high or the low part of a symbol address.
This isn't quite correct, however. It is valid -if unusual- assembler
to use, e.g.
li 1, symbol@ha
or
lis 1, symbol@l
Whether the high or the low part of the address is used depends solely
on the @ suffix, not on the instruction.
In addition, both
li 1, symbol
and
lis 1, symbol
are valid, assuming the symbol address fits into 16 bits; again, both
will then refer to the actual symbol value (so li will load the value
itself, while lis will load the value shifted by 16).
To fix this, two places need to be adapted. If the fixup cannot be
resolved at assembler time, a relocation needs to be emitted via
PPCELFObjectWriter::getRelocType. This routine already looks at
the VK_ type to determine the relocation. The only problem is that
will reject any _LO modifier in a ha16 fixup and vice versa. This
is simply incorrect; any of those modifiers ought to be accepted
for either fixup type.
If the fixup *can* be resolved at assembler time, adjustFixupValue
currently selects the high bits of the symbol value if the fixup
type is ha16. Again, this is incorrect; see the above example
lis 1, symbol
Now, in theory we'd have to respect a VK_ modifier here. However,
in fact common code never even attempts to resolve symbol references
using any nontrivial VK_ modifier at assembler time; it will always
fall back to emitting a reloc and letting the linker handle it.
If this ever changes, presumably there'd have to be a target callback
to resolve VK_ modifiers. We'd then have to handle @ha etc. there.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182091 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-17 12:36:29 +00:00
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# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_LO target 0x0
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lis 3, target@l
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# CHECK: li 3, target # encoding: [0x38,0x60,A,A]
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2013-05-17 12:37:21 +00:00
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# CHECK-NEXT: # fixup A - offset: 2, value: target, kind: fixup_ppc_half16
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[PowerPC] Fix processing of ha16/lo16 fixups
The current PowerPC MC back end distinguishes between fixup_ppc_ha16
and fixup_ppc_lo16, which are determined by the instruction the fixup
applies to, and uses this distinction to decide whether a fixup ought
to resolve to the high or the low part of a symbol address.
This isn't quite correct, however. It is valid -if unusual- assembler
to use, e.g.
li 1, symbol@ha
or
lis 1, symbol@l
Whether the high or the low part of the address is used depends solely
on the @ suffix, not on the instruction.
In addition, both
li 1, symbol
and
lis 1, symbol
are valid, assuming the symbol address fits into 16 bits; again, both
will then refer to the actual symbol value (so li will load the value
itself, while lis will load the value shifted by 16).
To fix this, two places need to be adapted. If the fixup cannot be
resolved at assembler time, a relocation needs to be emitted via
PPCELFObjectWriter::getRelocType. This routine already looks at
the VK_ type to determine the relocation. The only problem is that
will reject any _LO modifier in a ha16 fixup and vice versa. This
is simply incorrect; any of those modifiers ought to be accepted
for either fixup type.
If the fixup *can* be resolved at assembler time, adjustFixupValue
currently selects the high bits of the symbol value if the fixup
type is ha16. Again, this is incorrect; see the above example
lis 1, symbol
Now, in theory we'd have to respect a VK_ modifier here. However,
in fact common code never even attempts to resolve symbol references
using any nontrivial VK_ modifier at assembler time; it will always
fall back to emitting a reloc and letting the linker handle it.
If this ever changes, presumably there'd have to be a target callback
to resolve VK_ modifiers. We'd then have to handle @ha etc. there.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182091 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-17 12:36:29 +00:00
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# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16 target 0x0
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li 3, target
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# CHECK: lis 3, target # encoding: [0x3c,0x60,A,A]
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2013-05-17 12:37:21 +00:00
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# CHECK-NEXT: # fixup A - offset: 2, value: target, kind: fixup_ppc_half16
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[PowerPC] Fix processing of ha16/lo16 fixups
The current PowerPC MC back end distinguishes between fixup_ppc_ha16
and fixup_ppc_lo16, which are determined by the instruction the fixup
applies to, and uses this distinction to decide whether a fixup ought
to resolve to the high or the low part of a symbol address.
This isn't quite correct, however. It is valid -if unusual- assembler
to use, e.g.
li 1, symbol@ha
or
lis 1, symbol@l
Whether the high or the low part of the address is used depends solely
on the @ suffix, not on the instruction.
In addition, both
li 1, symbol
and
lis 1, symbol
are valid, assuming the symbol address fits into 16 bits; again, both
will then refer to the actual symbol value (so li will load the value
itself, while lis will load the value shifted by 16).
To fix this, two places need to be adapted. If the fixup cannot be
resolved at assembler time, a relocation needs to be emitted via
PPCELFObjectWriter::getRelocType. This routine already looks at
the VK_ type to determine the relocation. The only problem is that
will reject any _LO modifier in a ha16 fixup and vice versa. This
is simply incorrect; any of those modifiers ought to be accepted
for either fixup type.
If the fixup *can* be resolved at assembler time, adjustFixupValue
currently selects the high bits of the symbol value if the fixup
type is ha16. Again, this is incorrect; see the above example
lis 1, symbol
Now, in theory we'd have to respect a VK_ modifier here. However,
in fact common code never even attempts to resolve symbol references
using any nontrivial VK_ modifier at assembler time; it will always
fall back to emitting a reloc and letting the linker handle it.
If this ever changes, presumably there'd have to be a target callback
to resolve VK_ modifiers. We'd then have to handle @ha etc. there.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182091 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-17 12:36:29 +00:00
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# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16 target 0x0
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lis 3, target
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2013-06-21 14:42:49 +00:00
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# CHECK: li 3, target@h # encoding: [0x38,0x60,A,A]
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# CHECK-NEXT: # fixup A - offset: 2, value: target@h, kind: fixup_ppc_half16
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# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_HI target 0x0
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li 3, target@h
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# CHECK: lis 3, target@h # encoding: [0x3c,0x60,A,A]
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# CHECK-NEXT: # fixup A - offset: 2, value: target@h, kind: fixup_ppc_half16
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# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_HI target 0x0
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lis 3, target@h
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2013-06-21 14:43:42 +00:00
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# CHECK: li 3, target@higher # encoding: [0x38,0x60,A,A]
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# CHECK-NEXT: # fixup A - offset: 2, value: target@higher, kind: fixup_ppc_half16
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# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_HIGHER target 0x0
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li 3, target@higher
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# CHECK: lis 3, target@highest # encoding: [0x3c,0x60,A,A]
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# CHECK-NEXT: # fixup A - offset: 2, value: target@highest, kind: fixup_ppc_half16
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# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_HIGHEST target 0x0
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lis 3, target@highest
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# CHECK: li 3, target@highera # encoding: [0x38,0x60,A,A]
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# CHECK-NEXT: # fixup A - offset: 2, value: target@highera, kind: fixup_ppc_half16
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# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_HIGHERA target 0x0
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li 3, target@highera
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# CHECK: lis 3, target@highesta # encoding: [0x3c,0x60,A,A]
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# CHECK-NEXT: # fixup A - offset: 2, value: target@highesta, kind: fixup_ppc_half16
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# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_HIGHESTA target 0x0
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lis 3, target@highesta
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2013-05-03 19:52:35 +00:00
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# CHECK: lwz 1, target@l(3) # encoding: [0x80,0x23,A,A]
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2013-05-17 12:37:21 +00:00
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# CHECK-NEXT: # fixup A - offset: 2, value: target@l, kind: fixup_ppc_half16
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2013-05-15 15:07:06 +00:00
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# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_LO target 0x0
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2013-05-03 19:52:35 +00:00
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lwz 1, target@l(3)
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# CHECK: ld 1, target@l(3) # encoding: [0xe8,0x23,A,0bAAAAAA00]
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2013-05-17 12:37:21 +00:00
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# CHECK-NEXT: # fixup A - offset: 2, value: target@l, kind: fixup_ppc_half16ds
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2013-05-15 15:07:06 +00:00
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# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_ADDR16_LO_DS target 0x0
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2013-05-03 19:52:35 +00:00
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ld 1, target@l(3)
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# CHECK: ld 1, target@toc(2) # encoding: [0xe8,0x22,A,0bAAAAAA00]
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2013-05-17 12:37:21 +00:00
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# CHECK-NEXT: # fixup A - offset: 2, value: target@toc, kind: fixup_ppc_half16ds
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2013-05-15 15:07:06 +00:00
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# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TOC16_DS target 0x0
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2013-05-03 19:52:35 +00:00
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ld 1, target@toc(2)
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# CHECK: addis 3, 2, target@toc@ha # encoding: [0x3c,0x62,A,A]
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2013-05-17 12:37:21 +00:00
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# CHECK-NEXT: # fixup A - offset: 2, value: target@toc@ha, kind: fixup_ppc_half16
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2013-05-15 15:07:06 +00:00
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# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TOC16_HA target 0x0
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2013-05-03 19:52:35 +00:00
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addis 3, 2, target@toc@ha
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# CHECK: addi 4, 3, target@toc@l # encoding: [0x38,0x83,A,A]
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2013-05-17 12:37:21 +00:00
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# CHECK-NEXT: # fixup A - offset: 2, value: target@toc@l, kind: fixup_ppc_half16
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2013-05-15 15:07:06 +00:00
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# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TOC16_LO target 0x0
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2013-05-03 19:52:35 +00:00
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addi 4, 3, target@toc@l
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2013-06-21 14:43:10 +00:00
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# CHECK: addis 3, 2, target@toc@h # encoding: [0x3c,0x62,A,A]
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# CHECK-NEXT: # fixup A - offset: 2, value: target@toc@h, kind: fixup_ppc_half16
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# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TOC16_HI target 0x0
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addis 3, 2, target@toc@h
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2013-05-03 19:52:35 +00:00
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# CHECK: lwz 1, target@toc@l(3) # encoding: [0x80,0x23,A,A]
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2013-05-17 12:37:21 +00:00
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# CHECK-NEXT: # fixup A - offset: 2, value: target@toc@l, kind: fixup_ppc_half16
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2013-05-15 15:07:06 +00:00
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# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TOC16_LO target 0x0
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2013-05-03 19:52:35 +00:00
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lwz 1, target@toc@l(3)
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# CHECK: ld 1, target@toc@l(3) # encoding: [0xe8,0x23,A,0bAAAAAA00]
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2013-05-17 12:37:21 +00:00
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# CHECK-NEXT: # fixup A - offset: 2, value: target@toc@l, kind: fixup_ppc_half16ds
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2013-05-15 15:07:06 +00:00
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# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TOC16_LO_DS target 0x0
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2013-05-03 19:52:35 +00:00
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ld 1, target@toc@l(3)
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# FIXME: @tls
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# CHECK: addis 3, 2, target@tprel@ha # encoding: [0x3c,0x62,A,A]
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2013-05-17 12:37:21 +00:00
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# CHECK-NEXT: # fixup A - offset: 2, value: target@tprel@ha, kind: fixup_ppc_half16
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2013-05-15 15:07:06 +00:00
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# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TPREL16_HA target 0x0
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2013-05-03 19:52:35 +00:00
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addis 3, 2, target@tprel@ha
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# CHECK: addi 3, 3, target@tprel@l # encoding: [0x38,0x63,A,A]
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2013-05-17 12:37:21 +00:00
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# CHECK-NEXT: # fixup A - offset: 2, value: target@tprel@l, kind: fixup_ppc_half16
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2013-05-15 15:07:06 +00:00
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# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TPREL16_LO target 0x0
|
2013-05-03 19:52:35 +00:00
|
|
|
addi 3, 3, target@tprel@l
|
|
|
|
|
|
2013-06-21 14:44:15 +00:00
|
|
|
# CHECK: addi 3, 3, target@tprel # encoding: [0x38,0x63,A,A]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 2, value: target@tprel, kind: fixup_ppc_half16
|
|
|
|
|
# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TPREL16 target 0x0
|
|
|
|
|
addi 3, 3, target@tprel
|
|
|
|
|
|
|
|
|
|
# CHECK: addi 3, 3, target@tprel@h # encoding: [0x38,0x63,A,A]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 2, value: target@tprel@h, kind: fixup_ppc_half16
|
|
|
|
|
# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TPREL16_HI target 0x0
|
|
|
|
|
addi 3, 3, target@tprel@h
|
|
|
|
|
|
|
|
|
|
# CHECK: addi 3, 3, target@tprel@higher # encoding: [0x38,0x63,A,A]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 2, value: target@tprel@higher, kind: fixup_ppc_half16
|
|
|
|
|
# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TPREL16_HIGHER target 0x0
|
|
|
|
|
addi 3, 3, target@tprel@higher
|
|
|
|
|
|
|
|
|
|
# CHECK: addis 3, 2, target@tprel@highest # encoding: [0x3c,0x62,A,A]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 2, value: target@tprel@highest, kind: fixup_ppc_half16
|
|
|
|
|
# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TPREL16_HIGHEST target 0x0
|
|
|
|
|
addis 3, 2, target@tprel@highest
|
|
|
|
|
|
|
|
|
|
# CHECK: addi 3, 3, target@tprel@highera # encoding: [0x38,0x63,A,A]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 2, value: target@tprel@highera, kind: fixup_ppc_half16
|
|
|
|
|
# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TPREL16_HIGHERA target 0x0
|
|
|
|
|
addi 3, 3, target@tprel@highera
|
|
|
|
|
|
|
|
|
|
# CHECK: addis 3, 2, target@tprel@highesta # encoding: [0x3c,0x62,A,A]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 2, value: target@tprel@highesta, kind: fixup_ppc_half16
|
|
|
|
|
# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TPREL16_HIGHESTA target 0x0
|
|
|
|
|
addis 3, 2, target@tprel@highesta
|
|
|
|
|
|
|
|
|
|
# CHECK: ld 1, target@tprel@l(3) # encoding: [0xe8,0x23,A,0bAAAAAA00]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 2, value: target@tprel@l, kind: fixup_ppc_half16ds
|
|
|
|
|
# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TPREL16_LO_DS target 0x0
|
|
|
|
|
ld 1, target@tprel@l(3)
|
|
|
|
|
|
|
|
|
|
# CHECK: ld 1, target@tprel(3) # encoding: [0xe8,0x23,A,0bAAAAAA00]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 2, value: target@tprel, kind: fixup_ppc_half16ds
|
|
|
|
|
# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_TPREL16_DS target 0x0
|
|
|
|
|
ld 1, target@tprel(3)
|
|
|
|
|
|
2013-05-03 19:52:35 +00:00
|
|
|
# CHECK: addis 3, 2, target@dtprel@ha # encoding: [0x3c,0x62,A,A]
|
2013-05-17 12:37:21 +00:00
|
|
|
# CHECK-NEXT: # fixup A - offset: 2, value: target@dtprel@ha, kind: fixup_ppc_half16
|
2013-05-15 15:07:06 +00:00
|
|
|
# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_DTPREL16_HA target 0x0
|
2013-05-03 19:52:35 +00:00
|
|
|
addis 3, 2, target@dtprel@ha
|
|
|
|
|
|
|
|
|
|
# CHECK: addi 3, 3, target@dtprel@l # encoding: [0x38,0x63,A,A]
|
2013-05-17 12:37:21 +00:00
|
|
|
# CHECK-NEXT: # fixup A - offset: 2, value: target@dtprel@l, kind: fixup_ppc_half16
|
2013-05-15 15:07:06 +00:00
|
|
|
# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_DTPREL16_LO target 0x0
|
2013-05-03 19:52:35 +00:00
|
|
|
addi 3, 3, target@dtprel@l
|
|
|
|
|
|
2013-06-21 14:44:15 +00:00
|
|
|
# CHECK: addi 3, 3, target@dtprel # encoding: [0x38,0x63,A,A]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 2, value: target@dtprel, kind: fixup_ppc_half16
|
|
|
|
|
# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_DTPREL16 target 0x0
|
|
|
|
|
addi 3, 3, target@dtprel
|
|
|
|
|
|
|
|
|
|
# CHECK: addi 3, 3, target@dtprel@h # encoding: [0x38,0x63,A,A]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 2, value: target@dtprel@h, kind: fixup_ppc_half16
|
|
|
|
|
# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_DTPREL16_HI target 0x0
|
|
|
|
|
addi 3, 3, target@dtprel@h
|
|
|
|
|
|
|
|
|
|
# CHECK: addi 3, 3, target@dtprel@higher # encoding: [0x38,0x63,A,A]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 2, value: target@dtprel@higher, kind: fixup_ppc_half16
|
|
|
|
|
# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_DTPREL16_HIGHER target 0x0
|
|
|
|
|
addi 3, 3, target@dtprel@higher
|
|
|
|
|
|
|
|
|
|
# CHECK: addis 3, 2, target@dtprel@highest # encoding: [0x3c,0x62,A,A]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 2, value: target@dtprel@highest, kind: fixup_ppc_half16
|
|
|
|
|
# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_DTPREL16_HIGHEST target 0x0
|
|
|
|
|
addis 3, 2, target@dtprel@highest
|
|
|
|
|
|
|
|
|
|
# CHECK: addi 3, 3, target@dtprel@highera # encoding: [0x38,0x63,A,A]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 2, value: target@dtprel@highera, kind: fixup_ppc_half16
|
|
|
|
|
# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_DTPREL16_HIGHERA target 0x0
|
|
|
|
|
addi 3, 3, target@dtprel@highera
|
|
|
|
|
|
|
|
|
|
# CHECK: addis 3, 2, target@dtprel@highesta # encoding: [0x3c,0x62,A,A]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 2, value: target@dtprel@highesta, kind: fixup_ppc_half16
|
|
|
|
|
# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_DTPREL16_HIGHESTA target 0x0
|
|
|
|
|
addis 3, 2, target@dtprel@highesta
|
|
|
|
|
|
|
|
|
|
# CHECK: ld 1, target@dtprel@l(3) # encoding: [0xe8,0x23,A,0bAAAAAA00]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 2, value: target@dtprel@l, kind: fixup_ppc_half16ds
|
|
|
|
|
# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_DTPREL16_LO_DS target 0x0
|
|
|
|
|
ld 1, target@dtprel@l(3)
|
|
|
|
|
|
|
|
|
|
# CHECK: ld 1, target@dtprel(3) # encoding: [0xe8,0x23,A,0bAAAAAA00]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 2, value: target@dtprel, kind: fixup_ppc_half16ds
|
|
|
|
|
# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_DTPREL16_DS target 0x0
|
|
|
|
|
ld 1, target@dtprel(3)
|
|
|
|
|
|
2013-05-03 19:52:35 +00:00
|
|
|
|
|
|
|
|
# CHECK: addis 3, 2, target@got@tprel@ha # encoding: [0x3c,0x62,A,A]
|
2013-05-17 12:37:21 +00:00
|
|
|
# CHECK-NEXT: # fixup A - offset: 2, value: target@got@tprel@ha, kind: fixup_ppc_half16
|
2013-05-15 15:07:06 +00:00
|
|
|
# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TPREL16_HA target 0x0
|
2013-05-03 19:52:35 +00:00
|
|
|
addis 3, 2, target@got@tprel@ha
|
|
|
|
|
|
|
|
|
|
# CHECK: ld 1, target@got@tprel@l(3) # encoding: [0xe8,0x23,A,0bAAAAAA00]
|
2013-05-17 12:37:21 +00:00
|
|
|
# CHECK-NEXT: # fixup A - offset: 2, value: target@got@tprel@l, kind: fixup_ppc_half16ds
|
2013-05-15 15:07:06 +00:00
|
|
|
# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TPREL16_LO_DS target 0x0
|
2013-05-03 19:52:35 +00:00
|
|
|
ld 1, target@got@tprel@l(3)
|
|
|
|
|
|
2013-06-21 14:44:15 +00:00
|
|
|
# CHECK: addis 3, 2, target@got@tprel@h # encoding: [0x3c,0x62,A,A]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 2, value: target@got@tprel@h, kind: fixup_ppc_half16
|
|
|
|
|
# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TPREL16_HI target 0x0
|
|
|
|
|
addis 3, 2, target@got@tprel@h
|
|
|
|
|
|
|
|
|
|
# CHECK: ld 1, target@got@tprel(3) # encoding: [0xe8,0x23,A,0bAAAAAA00]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 2, value: target@got@tprel, kind: fixup_ppc_half16ds
|
|
|
|
|
# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TPREL16_DS target 0x0
|
|
|
|
|
ld 1, target@got@tprel(3)
|
|
|
|
|
|
|
|
|
|
# CHECK: addis 3, 2, target@got@dtprel@ha # encoding: [0x3c,0x62,A,A]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 2, value: target@got@dtprel@ha, kind: fixup_ppc_half16
|
|
|
|
|
# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_DTPREL16_HA target 0x0
|
|
|
|
|
addis 3, 2, target@got@dtprel@ha
|
|
|
|
|
|
|
|
|
|
# CHECK: ld 1, target@got@dtprel@l(3) # encoding: [0xe8,0x23,A,0bAAAAAA00]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 2, value: target@got@dtprel@l, kind: fixup_ppc_half16ds
|
|
|
|
|
# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_DTPREL16_LO_DS target 0x0
|
|
|
|
|
ld 1, target@got@dtprel@l(3)
|
|
|
|
|
|
|
|
|
|
# CHECK: addis 3, 2, target@got@dtprel@h # encoding: [0x3c,0x62,A,A]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 2, value: target@got@dtprel@h, kind: fixup_ppc_half16
|
|
|
|
|
# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_DTPREL16_HI target 0x0
|
|
|
|
|
addis 3, 2, target@got@dtprel@h
|
|
|
|
|
|
|
|
|
|
# CHECK: ld 1, target@got@dtprel(3) # encoding: [0xe8,0x23,A,0bAAAAAA00]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 2, value: target@got@dtprel, kind: fixup_ppc_half16ds
|
|
|
|
|
# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_DTPREL16_DS target 0x0
|
|
|
|
|
ld 1, target@got@dtprel(3)
|
2013-05-03 19:52:35 +00:00
|
|
|
|
|
|
|
|
# CHECK: addis 3, 2, target@got@tlsgd@ha # encoding: [0x3c,0x62,A,A]
|
2013-05-17 12:37:21 +00:00
|
|
|
# CHECK-NEXT: # fixup A - offset: 2, value: target@got@tlsgd@ha, kind: fixup_ppc_half16
|
2013-05-15 15:07:06 +00:00
|
|
|
# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TLSGD16_HA target 0x0
|
2013-05-03 19:52:35 +00:00
|
|
|
addis 3, 2, target@got@tlsgd@ha
|
|
|
|
|
|
|
|
|
|
# CHECK: addi 3, 3, target@got@tlsgd@l # encoding: [0x38,0x63,A,A]
|
2013-05-17 12:37:21 +00:00
|
|
|
# CHECK-NEXT: # fixup A - offset: 2, value: target@got@tlsgd@l, kind: fixup_ppc_half16
|
2013-05-15 15:07:06 +00:00
|
|
|
# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TLSGD16_LO target 0x0
|
2013-05-03 19:52:35 +00:00
|
|
|
addi 3, 3, target@got@tlsgd@l
|
|
|
|
|
|
2013-06-21 14:44:15 +00:00
|
|
|
# CHECK: addi 3, 3, target@got@tlsgd@h # encoding: [0x38,0x63,A,A]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 2, value: target@got@tlsgd@h, kind: fixup_ppc_half16
|
|
|
|
|
# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TLSGD16_HI target 0x0
|
|
|
|
|
addi 3, 3, target@got@tlsgd@h
|
|
|
|
|
|
|
|
|
|
# CHECK: addi 3, 3, target@got@tlsgd # encoding: [0x38,0x63,A,A]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 2, value: target@got@tlsgd, kind: fixup_ppc_half16
|
|
|
|
|
# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TLSGD16 target 0x0
|
|
|
|
|
addi 3, 3, target@got@tlsgd
|
|
|
|
|
|
2013-05-03 19:52:35 +00:00
|
|
|
|
|
|
|
|
# CHECK: addis 3, 2, target@got@tlsld@ha # encoding: [0x3c,0x62,A,A]
|
2013-05-17 12:37:21 +00:00
|
|
|
# CHECK-NEXT: # fixup A - offset: 2, value: target@got@tlsld@ha, kind: fixup_ppc_half16
|
2013-05-15 15:07:06 +00:00
|
|
|
# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TLSLD16_HA target 0x0
|
2013-05-03 19:52:35 +00:00
|
|
|
addis 3, 2, target@got@tlsld@ha
|
|
|
|
|
|
|
|
|
|
# CHECK: addi 3, 3, target@got@tlsld@l # encoding: [0x38,0x63,A,A]
|
2013-05-17 12:37:21 +00:00
|
|
|
# CHECK-NEXT: # fixup A - offset: 2, value: target@got@tlsld@l, kind: fixup_ppc_half16
|
2013-05-15 15:07:06 +00:00
|
|
|
# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TLSLD16_LO target 0x0
|
2013-05-03 19:52:35 +00:00
|
|
|
addi 3, 3, target@got@tlsld@l
|
|
|
|
|
|
2013-06-21 14:44:15 +00:00
|
|
|
# CHECK: addi 3, 3, target@got@tlsld@h # encoding: [0x38,0x63,A,A]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 2, value: target@got@tlsld@h, kind: fixup_ppc_half16
|
|
|
|
|
# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TLSLD16_HI target 0x0
|
|
|
|
|
addi 3, 3, target@got@tlsld@h
|
|
|
|
|
|
|
|
|
|
# CHECK: addi 3, 3, target@got@tlsld # encoding: [0x38,0x63,A,A]
|
|
|
|
|
# CHECK-NEXT: # fixup A - offset: 2, value: target@got@tlsld, kind: fixup_ppc_half16
|
|
|
|
|
# CHECK-REL: 0x{{[0-9A-F]*[26AE]}} R_PPC64_GOT_TLSLD16 target 0x0
|
|
|
|
|
addi 3, 3, target@got@tlsld
|
|
|
|
|
|