6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-12-28 19:31:58 +00:00
Code Issues Projects Releases Wiki Activity
d4daf1762d
llvm-6502/test/MC/Mips/mips-jump-instructions.s

159 lines
7.5 KiB
ArmAsm
Raw Normal View History

[Mips Assembler] Add alias definitions for jal Mips assembler allows following to be used as aliased instructions: jal $rs for jalr $rs jal $rd,$rd for jalr $rd,$rs This patch provides alias definitions in td files and test cases to show the usage. Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178304 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-28 23:02:21 +00:00
# RUN: llvm-mc %s -triple=mipsel-unknown-linux -show-encoding -mcpu=mips32r2 | \
Mips assembler: Add 64 bit testing for JAL Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180220 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-24 21:52:42 +00:00
# RUN: FileCheck -check-prefix=CHECK32 %s
[mips] Print instructions "beq", "bne" and "or" using assembler pseudo instructions "beqz", "bnez" and "move", when possible. beq $2, $zero, $L1 => beqz $2, $L1 bne $2, $zero, $L1 => bnez $2, $L1 or $2, $3, $zero => move $2, $3 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187229 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-26 18:34:25 +00:00
# RUN: llvm-mc %s -triple=mips64el-unknown-linux -show-encoding -mcpu=mips64r2 | \
Mips assembler: Add 64 bit testing for JAL Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180220 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-24 21:52:42 +00:00
# RUN: FileCheck -check-prefix=CHECK64 %s
Mips specific llvm assembler support for branch and jump instructions. Test case included. Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163277 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-06 00:43:26 +00:00
# Check that the assembler can handle the documented syntax
# for jumps and branches.
#------------------------------------------------------------------------------
# Branch instructions
#------------------------------------------------------------------------------
Mips assembler: Add 64 bit testing for JAL Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180220 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-24 21:52:42 +00:00
# CHECK32: b 1332 # encoding: [0x4d,0x01,0x00,0x10]
# CHECK32: nop # encoding: [0x00,0x00,0x00,0x00]
# CHECK32: bc1f 1332 # encoding: [0x4d,0x01,0x00,0x45]
# CHECK32: nop # encoding: [0x00,0x00,0x00,0x00]
# CHECK32: bc1t 1332 # encoding: [0x4d,0x01,0x01,0x45]
# CHECK32: nop # encoding: [0x00,0x00,0x00,0x00]
# CHECK32: beq $9, $6, 1332 # encoding: [0x4d,0x01,0x26,0x11]
# CHECK32: nop # encoding: [0x00,0x00,0x00,0x00]
# CHECK32: bgez $6, 1332 # encoding: [0x4d,0x01,0xc1,0x04]
# CHECK32: nop # encoding: [0x00,0x00,0x00,0x00]
# CHECK32: bgezal $6, 1332 # encoding: [0x4d,0x01,0xd1,0x04]
# CHECK32: nop # encoding: [0x00,0x00,0x00,0x00]
# CHECK32: bgtz $6, 1332 # encoding: [0x4d,0x01,0xc0,0x1c]
# CHECK32: nop # encoding: [0x00,0x00,0x00,0x00]
# CHECK32: blez $6, 1332 # encoding: [0x4d,0x01,0xc0,0x18]
# CHECK32: nop # encoding: [0x00,0x00,0x00,0x00]
# CHECK32: bne $9, $6, 1332 # encoding: [0x4d,0x01,0x26,0x15]
# CHECK32: nop # encoding: [0x00,0x00,0x00,0x00]
Mips assembler: Add branch macro definitions This patch adds bnez and beqz instructions which represent alias definitions for bne and beq instructions as follows: bnez $rs,$imm => bne $rs,$zero,$imm beqz $rs,$imm => beq $rs,$zero,$imm The corresponding test cases are added. Patch by Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182040 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-16 19:40:19 +00:00
# CHECK32: bal 1332 # encoding: [0x4d,0x01,0x11,0x04]
# CHECK32: nop # encoding: [0x00,0x00,0x00,0x00]
[mips] Print instructions "beq", "bne" and "or" using assembler pseudo instructions "beqz", "bnez" and "move", when possible. beq $2, $zero, $L1 => beqz $2, $L1 bne $2, $zero, $L1 => bnez $2, $L1 or $2, $3, $zero => move $2, $3 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187229 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-26 18:34:25 +00:00
# CHECK32: bnez $11, 1332 # encoding: [0x4d,0x01,0x60,0x15]
Mips assembler: Add branch macro definitions This patch adds bnez and beqz instructions which represent alias definitions for bne and beq instructions as follows: bnez $rs,$imm => bne $rs,$zero,$imm beqz $rs,$imm => beq $rs,$zero,$imm The corresponding test cases are added. Patch by Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182040 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-16 19:40:19 +00:00
# CHECK32: nop # encoding: [0x00,0x00,0x00,0x00]
[mips] Print instructions "beq", "bne" and "or" using assembler pseudo instructions "beqz", "bnez" and "move", when possible. beq $2, $zero, $L1 => beqz $2, $L1 bne $2, $zero, $L1 => bnez $2, $L1 or $2, $3, $zero => move $2, $3 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187229 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-26 18:34:25 +00:00
# CHECK32: beqz $11, 1332 # encoding: [0x4d,0x01,0x60,0x11]
Mips assembler: Add 64 bit testing for JAL Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180220 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-24 21:52:42 +00:00
# CHECK32: nop # encoding: [0x00,0x00,0x00,0x00]
# CHECK64: b 1332 # encoding: [0x4d,0x01,0x00,0x10]
# CHECK64: nop # encoding: [0x00,0x00,0x00,0x00]
# CHECK64: bc1f 1332 # encoding: [0x4d,0x01,0x00,0x45]
# CHECK64: nop # encoding: [0x00,0x00,0x00,0x00]
# CHECK64: bc1t 1332 # encoding: [0x4d,0x01,0x01,0x45]
# CHECK64: nop # encoding: [0x00,0x00,0x00,0x00]
# CHECK64: beq $9, $6, 1332 # encoding: [0x4d,0x01,0x26,0x11]
# CHECK64: nop # encoding: [0x00,0x00,0x00,0x00]
# CHECK64: bgez $6, 1332 # encoding: [0x4d,0x01,0xc1,0x04]
# CHECK64: nop # encoding: [0x00,0x00,0x00,0x00]
# CHECK64: bgezal $6, 1332 # encoding: [0x4d,0x01,0xd1,0x04]
# CHECK64: nop # encoding: [0x00,0x00,0x00,0x00]
# CHECK64: bgtz $6, 1332 # encoding: [0x4d,0x01,0xc0,0x1c]
# CHECK64: nop # encoding: [0x00,0x00,0x00,0x00]
# CHECK64: blez $6, 1332 # encoding: [0x4d,0x01,0xc0,0x18]
# CHECK64: nop # encoding: [0x00,0x00,0x00,0x00]
# CHECK64: bne $9, $6, 1332 # encoding: [0x4d,0x01,0x26,0x15]
# CHECK64: nop # encoding: [0x00,0x00,0x00,0x00]
# CHECK64: bal 1332 # encoding: [0x4d,0x01,0x11,0x04]
# CHECK64: nop # encoding: [0x00,0x00,0x00,0x00]
[mips] Print instructions "beq", "bne" and "or" using assembler pseudo instructions "beqz", "bnez" and "move", when possible. beq $2, $zero, $L1 => beqz $2, $L1 bne $2, $zero, $L1 => bnez $2, $L1 or $2, $3, $zero => move $2, $3 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187229 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-26 18:34:25 +00:00
# CHECK64: bnez $11, 1332 # encoding: [0x4d,0x01,0x60,0x15]
Mips assembler: Add branch macro definitions This patch adds bnez and beqz instructions which represent alias definitions for bne and beq instructions as follows: bnez $rs,$imm => bne $rs,$zero,$imm beqz $rs,$imm => beq $rs,$zero,$imm The corresponding test cases are added. Patch by Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182040 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-16 19:40:19 +00:00
# CHECK64: nop # encoding: [0x00,0x00,0x00,0x00]
[mips] Print instructions "beq", "bne" and "or" using assembler pseudo instructions "beqz", "bnez" and "move", when possible. beq $2, $zero, $L1 => beqz $2, $L1 bne $2, $zero, $L1 => bnez $2, $L1 or $2, $3, $zero => move $2, $3 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187229 91177308-0d34-0410-b5e6-96231b3b80d8
2013-07-26 18:34:25 +00:00
# CHECK64: beqz $11, 1332 # encoding: [0x4d,0x01,0x60,0x11]
Mips assembler: Add branch macro definitions This patch adds bnez and beqz instructions which represent alias definitions for bne and beq instructions as follows: bnez $rs,$imm => bne $rs,$zero,$imm beqz $rs,$imm => beq $rs,$zero,$imm The corresponding test cases are added. Patch by Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182040 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-16 19:40:19 +00:00
# CHECK64: nop # encoding: [0x00,0x00,0x00,0x00]
[Mips Assembler] Add alias definitions for jal Mips assembler allows following to be used as aliased instructions: jal $rs for jalr $rs jal $rd,$rd for jalr $rd,$rs This patch provides alias definitions in td files and test cases to show the usage. Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178304 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-28 23:02:21 +00:00
.set noreorder
Mips specific llvm assembler support for branch and jump instructions. Test case included. Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163277 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-06 00:43:26 +00:00
b 1332
nop
bc1f 1332
nop
bc1t 1332
nop
beq $9,$6,1332
nop
bgez $6,1332
nop
bgezal $6,1332
nop
bgtz $6,1332
nop
blez $6,1332
nop
bne $9,$6,1332
nop
The Mips standalone assembler aliased instruction support. The assembler can alias one instruction into another based on the operands. For example the jump instruction "J" takes and immediate operand, but if the operand is a register the assembler will change it into a jump register "JR" instruction. These changes are in the instruction td file. Test cases included Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163368 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-07 01:42:38 +00:00
bal 1332
nop
Mips assembler: Add branch macro definitions This patch adds bnez and beqz instructions which represent alias definitions for bne and beq instructions as follows: bnez $rs,$imm => bne $rs,$zero,$imm beqz $rs,$imm => beq $rs,$zero,$imm The corresponding test cases are added. Patch by Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182040 91177308-0d34-0410-b5e6-96231b3b80d8
2013-05-16 19:40:19 +00:00
bnez $11,1332
nop
beqz $11,1332
nop
Mips specific llvm assembler support for branch and jump instructions. Test case included. Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163277 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-06 00:43:26 +00:00
end_of_code:
#------------------------------------------------------------------------------
# Jump instructions
#------------------------------------------------------------------------------
Mips assembler: Add 64 bit testing for JAL Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180220 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-24 21:52:42 +00:00
# CHECK32: j 1328 # encoding: [0x4c,0x01,0x00,0x08]
# CHECK32: nop # encoding: [0x00,0x00,0x00,0x00]
# CHECK32: jal 1328 # encoding: [0x4c,0x01,0x00,0x0c]
# CHECK32: nop # encoding: [0x00,0x00,0x00,0x00]
# CHECK32: jalr $6 # encoding: [0x09,0xf8,0xc0,0x00]
# CHECK32: nop # encoding: [0x00,0x00,0x00,0x00]
# CHECK32: jalr $25 # encoding: [0x09,0xf8,0x20,0x03]
# CHECK32: nop # encoding: [0x00,0x00,0x00,0x00]
# CHECK32: jalr $10, $11 # encoding: [0x09,0x50,0x60,0x01]
# CHECK32: nop # encoding: [0x00,0x00,0x00,0x00]
# CHECK32: jr $7 # encoding: [0x08,0x00,0xe0,0x00]
# CHECK32: nop # encoding: [0x00,0x00,0x00,0x00]
This patch implements jalx instruction for Mips architecture.This instruction executes a procedure call within the current 256 MB-aligned region and change the ISA Mode from MIPS32 to microMIPS32 or MIPS16e. Usage samples for assembler and dissasembler are provided as well. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202706 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-03 13:12:59 +00:00
# CHECK32:lab:
Mips assembler: Add 64 bit testing for JAL Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180220 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-24 21:52:42 +00:00
# CHECK32: jr $7 # encoding: [0x08,0x00,0xe0,0x00]
# CHECK32: nop # encoding: [0x00,0x00,0x00,0x00]
# CHECK32: jalr $25 # encoding: [0x09,0xf8,0x20,0x03]
# CHECK32: nop # encoding: [0x00,0x00,0x00,0x00]
# CHECK32: jalr $4, $25 # encoding: [0x09,0x20,0x20,0x03]
# CHECK32: nop # encoding: [0x00,0x00,0x00,0x00]
This patch implements jalx instruction for Mips architecture.This instruction executes a procedure call within the current 256 MB-aligned region and change the ISA Mode from MIPS32 to microMIPS32 or MIPS16e. Usage samples for assembler and dissasembler are provided as well. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202706 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-03 13:12:59 +00:00
# CHECK32: jalx lab # encoding: [A,A,A,0b011101AA]
# CHECK32: # fixup A - offset: 0, value: lab, kind: fixup_Mips_26
# CHECK32: nop # encoding: [0x00,0x00,0x00,0x00]
Mips assembler: Add 64 bit testing for JAL Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180220 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-24 21:52:42 +00:00
# CHECK64: j 1328 # encoding: [0x4c,0x01,0x00,0x08]
# CHECK64: nop # encoding: [0x00,0x00,0x00,0x00]
# CHECK64: jal 1328 # encoding: [0x4c,0x01,0x00,0x0c]
# CHECK64: nop # encoding: [0x00,0x00,0x00,0x00]
# CHECK64: jalr $6 # encoding: [0x09,0xf8,0xc0,0x00]
# CHECK64: nop # encoding: [0x00,0x00,0x00,0x00]
# CHECK64: jalr $25 # encoding: [0x09,0xf8,0x20,0x03]
# CHECK64: nop # encoding: [0x00,0x00,0x00,0x00]
# CHECK64: jalr $10, $11 # encoding: [0x09,0x50,0x60,0x01]
# CHECK64: nop # encoding: [0x00,0x00,0x00,0x00]
# CHECK64: jr $7 # encoding: [0x08,0x00,0xe0,0x00]
# CHECK64: nop # encoding: [0x00,0x00,0x00,0x00]
This patch implements jalx instruction for Mips architecture.This instruction executes a procedure call within the current 256 MB-aligned region and change the ISA Mode from MIPS32 to microMIPS32 or MIPS16e. Usage samples for assembler and dissasembler are provided as well. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202706 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-03 13:12:59 +00:00
# CHECK64:lab:
Mips assembler: Add 64 bit testing for JAL Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180220 91177308-0d34-0410-b5e6-96231b3b80d8
2013-04-24 21:52:42 +00:00
# CHECK64: jr $7 # encoding: [0x08,0x00,0xe0,0x00]
# CHECK64: nop # encoding: [0x00,0x00,0x00,0x00]
# CHECK64: jalr $25 # encoding: [0x09,0xf8,0x20,0x03]
# CHECK64: nop # encoding: [0x00,0x00,0x00,0x00]
# CHECK64: jalr $4, $25 # encoding: [0x09,0x20,0x20,0x03]
# CHECK64: nop # encoding: [0x00,0x00,0x00,0x00]
This patch implements jalx instruction for Mips architecture.This instruction executes a procedure call within the current 256 MB-aligned region and change the ISA Mode from MIPS32 to microMIPS32 or MIPS16e. Usage samples for assembler and dissasembler are provided as well. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202706 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-03 13:12:59 +00:00
# CHECK64: jalx lab # encoding: [A,A,A,0b011101AA]
# CHECK64: # fixup A - offset: 0, value: lab, kind: fixup_Mips_26
# CHECK64: nop # encoding: [0x00,0x00,0x00,0x00]
Mips specific llvm assembler support for branch and jump instructions. Test case included. Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163277 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-06 00:43:26 +00:00
j 1328
nop
jal 1328
nop
jalr $6
nop
[mips] Add definition of JALR instruction which has two register operands. Change the original JALR instruction with one register operand to be a pseudo-instruction. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174657 91177308-0d34-0410-b5e6-96231b3b80d8
2013-02-07 19:48:00 +00:00
jalr $31, $25
nop
jalr $10, $11
nop
Mips specific llvm assembler support for branch and jump instructions. Test case included. Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163277 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-06 00:43:26 +00:00
jr $7
The Mips standalone assembler aliased instruction support. The assembler can alias one instruction into another based on the operands. For example the jump instruction "J" takes and immediate operand, but if the operand is a register the assembler will change it into a jump register "JR" instruction. These changes are in the instruction td file. Test cases included Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163368 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-07 01:42:38 +00:00
nop
This patch implements jalx instruction for Mips architecture.This instruction executes a procedure call within the current 256 MB-aligned region and change the ISA Mode from MIPS32 to microMIPS32 or MIPS16e. Usage samples for assembler and dissasembler are provided as well. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202706 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-03 13:12:59 +00:00
lab:
The Mips standalone assembler aliased instruction support. The assembler can alias one instruction into another based on the operands. For example the jump instruction "J" takes and immediate operand, but if the operand is a register the assembler will change it into a jump register "JR" instruction. These changes are in the instruction td file. Test cases included Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163368 91177308-0d34-0410-b5e6-96231b3b80d8
2012-09-07 01:42:38 +00:00
j $7
[Mips Assembler] Add alias definitions for jal Mips assembler allows following to be used as aliased instructions: jal $rs for jalr $rs jal $rd,$rd for jalr $rd,$rs This patch provides alias definitions in td files and test cases to show the usage. Contributer: Vladimir Medic git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178304 91177308-0d34-0410-b5e6-96231b3b80d8
2013-03-28 23:02:21 +00:00
nop
jal $25
nop
jal $4,$25
nop
This patch implements jalx instruction for Mips architecture.This instruction executes a procedure call within the current 256 MB-aligned region and change the ISA Mode from MIPS32 to microMIPS32 or MIPS16e. Usage samples for assembler and dissasembler are provided as well. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@202706 91177308-0d34-0410-b5e6-96231b3b80d8
2014-03-03 13:12:59 +00:00
jalx lab
nop
Reference in New Issue Copy Permalink