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< title > The LLVM Target-Independent Code Generator< / title >
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The LLVM Target-Independent Code Generator
< / div >
< ol >
< li > < a href = "#introduction" > Introduction< / a >
< ul >
< li > < a href = "#required" > Required components in the code generator< / a > < / li >
< li > < a href = "#high-level-design" > The high-level design of the code generator< / a > < / li >
< li > < a href = "#tablegen" > Using TableGen for target description< / a > < / li >
< / ul >
< / li >
< li > < a href = "#targetdesc" > Target description classes< / a >
< ul >
< li > < a href = "#targetmachine" > The < tt > TargetMachine< / tt > class< / a > < / li >
< li > < a href = "#targetdata" > The < tt > TargetData< / tt > class< / a > < / li >
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< li > < a href = "#targetlowering" > The < tt > TargetLowering< / tt > class< / a > < / li >
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< li > < a href = "#mregisterinfo" > The < tt > MRegisterInfo< / tt > class< / a > < / li >
< li > < a href = "#targetinstrinfo" > The < tt > TargetInstrInfo< / tt > class< / a > < / li >
< li > < a href = "#targetframeinfo" > The < tt > TargetFrameInfo< / tt > class< / a > < / li >
< li > < a href = "#targetjitinfo" > The < tt > TargetJITInfo< / tt > class< / a > < / li >
< / ul >
< / li >
< li > < a href = "#codegendesc" > Machine code description classes< / a >
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< ul >
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< li > < a href = "#machineinstr" > The < tt > MachineInstr< / tt > class< / a > < / li >
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< / ul >
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< / li >
< li > < a href = "#codegenalgs" > Target-independent code generation algorithms< / a >
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< ul >
< li > < a href = "#instselect" > Instruction Selection< / a >
< ul >
< li > < a href = "#selectiondag_intro" > Introduction to SelectionDAGs< / a > < / li >
< li > < a href = "#selectiondag_process" > SelectionDAG Code Generation
Process< / a > < / li >
< li > < a href = "#selectiondag_build" > Initial SelectionDAG
Construction< / a > < / li >
< li > < a href = "#selectiondag_legalize" > SelectionDAG Legalize Phase< / a > < / li >
< li > < a href = "#selectiondag_optimize" > SelectionDAG Optimization
Phase< / a > < / li >
< li > < a href = "#selectiondag_select" > SelectionDAG Select Phase< / a > < / li >
< li > < a href = "#selectiondag_future" > Future directions for the
SelectionDAG< / a > < / li >
< / ul > < / li >
< / ul >
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< / li >
< li > < a href = "#targetimpls" > Target description implementations< / a >
< ul >
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< li > < a href = "#x86" > The X86 backend< / a > < / li >
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< / ul >
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< / li >
< / ol >
< div class = "doc_author" >
< p > Written by < a href = "mailto:sabre@nondot.org" > Chris Lattner< / a > < / p >
< / div >
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< div class = "doc_warning" >
< p > Warning: This is a work in progress.< / p >
< / div >
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<!-- *********************************************************************** -->
< div class = "doc_section" >
< a name = "introduction" > Introduction< / a >
< / div >
<!-- *********************************************************************** -->
< div class = "doc_text" >
< p > The LLVM target-independent code generator is a framework that provides a
suite of reusable components for translating the LLVM internal representation to
the machine code for a specified target -- either in assembly form (suitable for
a static compiler) or in binary machine code format (usable for a JIT compiler).
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The LLVM target-independent code generator consists of five main components:< / p >
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< ol >
< li > < a href = "#targetdesc" > Abstract target description< / a > interfaces which
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capture important properties about various aspects of the machine, independently
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of how they will be used. These interfaces are defined in
< tt > include/llvm/Target/< / tt > .< / li >
< li > Classes used to represent the < a href = "#codegendesc" > machine code< / a > being
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generated for a target. These classes are intended to be abstract enough to
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represent the machine code for < i > any< / i > target machine. These classes are
defined in < tt > include/llvm/CodeGen/< / tt > .< / li >
< li > < a href = "#codegenalgs" > Target-independent algorithms< / a > used to implement
various phases of native code generation (register allocation, scheduling, stack
frame representation, etc). This code lives in < tt > lib/CodeGen/< / tt > .< / li >
< li > < a href = "#targetimpls" > Implementations of the abstract target description
interfaces< / a > for particular targets. These machine descriptions make use of
the components provided by LLVM, and can optionally provide custom
target-specific passes, to build complete code generators for a specific target.
Target descriptions live in < tt > lib/Target/< / tt > .< / li >
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< li > < a href = "#jit" > The target-independent JIT components< / a > . The LLVM JIT is
completely target independent (it uses the < tt > TargetJITInfo< / tt > structure to
interface for target-specific issues. The code for the target-independent
JIT lives in < tt > lib/ExecutionEngine/JIT< / tt > .< / li >
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< / ol >
< p >
Depending on which part of the code generator you are interested in working on,
different pieces of this will be useful to you. In any case, you should be
familiar with the < a href = "#targetdesc" > target description< / a > and < a
href="#codegendesc">machine code representation< / a > classes. If you want to add
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a backend for a new target, you will need to < a href = "#targetimpls" > implement the
target description< / a > classes for your new target and understand the < a
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href="LangRef.html">LLVM code representation< / a > . If you are interested in
implementing a new < a href = "#codegenalgs" > code generation algorithm< / a > , it
should only depend on the target-description and machine code representation
classes, ensuring that it is portable.
< / p >
< / div >
<!-- ======================================================================= -->
< div class = "doc_subsection" >
< a name = "required" > Required components in the code generator< / a >
< / div >
< div class = "doc_text" >
< p > The two pieces of the LLVM code generator are the high-level interface to the
code generator and the set of reusable components that can be used to build
target-specific backends. The two most important interfaces (< a
href="#targetmachine">< tt > TargetMachine< / tt > < / a > and < a
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href="#targetdata">< tt > TargetData< / tt > < / a > ) are the only ones that are
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required to be defined for a backend to fit into the LLVM system, but the others
must be defined if the reusable code generator components are going to be
used.< / p >
< p > This design has two important implications. The first is that LLVM can
support completely non-traditional code generation targets. For example, the C
backend does not require register allocation, instruction selection, or any of
the other standard components provided by the system. As such, it only
implements these two interfaces, and does its own thing. Another example of a
code generator like this is a (purely hypothetical) backend that converts LLVM
to the GCC RTL form and uses GCC to emit machine code for a target.< / p >
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< p > This design also implies that it is possible to design and
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implement radically different code generators in the LLVM system that do not
make use of any of the built-in components. Doing so is not recommended at all,
but could be required for radically different targets that do not fit into the
LLVM machine description model: programmable FPGAs for example.< / p >
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< p > < b > Important Note:< / b > For historical reasons, the LLVM SparcV9 code
generator uses almost entirely different code paths than described in this
document. For this reason, there are some deprecated interfaces (such as
< tt > TargetRegInfo< / tt > and < tt > TargetSchedInfo< / tt > ), which are only used by the
V9 backend and should not be used by any other targets. Also, all code in the
< tt > lib/Target/SparcV9< / tt > directory and subdirectories should be considered
deprecated, and should not be used as the basis for future code generator work.
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The SparcV9 backend is slowly being merged into the rest of the
target-independent code generators, but this is a low-priority process with no
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predictable completion date.< / p >
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< / div >
<!-- ======================================================================= -->
< div class = "doc_subsection" >
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< a name = "high-level-design" > The high-level design of the code generator< / a >
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< / div >
< div class = "doc_text" >
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< p > The LLVM target-independent code generator is designed to support efficient and
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quality code generation for standard register-based microprocessors. Code
generation in this model is divided into the following stages:< / p >
< ol >
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< li > < b > < a href = "#instselect" > Instruction Selection< / a > < / b > - Determining an
efficient implementation of the input LLVM code in the target instruction set.
This stage produces the initial code for the program in the target instruction
set, then makes use of virtual registers in SSA form and physical registers that
represent any required register assignments due to target constraints or calling
conventions.< / li >
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< li > < b > < a href = "#ssamco" > SSA-based Machine Code Optimizations< / a > < / b > - This
optional stage consists of a series of machine-code optimizations that
operate on the SSA-form produced by the instruction selector. Optimizations
like modulo-scheduling, normal scheduling, or peephole optimization work here.
< / li >
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< li > < b > < a name = "#regalloc" > Register Allocation< / a > < / b > - The
target code is transformed from an infinite virtual register file in SSA form
to the concrete register file used by the target. This phase introduces spill
code and eliminates all virtual register references from the program.< / li >
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< li > < b > < a name = "#proepicode" > Prolog/Epilog Code Insertion< / a > < / b > - Once the
machine code has been generated for the function and the amount of stack space
required is known (used for LLVM alloca's and spill slots), the prolog and
epilog code for the function can be inserted and "abstract stack location
references" can be eliminated. This stage is responsible for implementing
optimizations like frame-pointer elimination and stack packing.< / li >
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< li > < b > < a name = "latemco" > Late Machine Code Optimizations< / a > < / b > - Optimizations
that operate on "final" machine code can go here, such as spill code scheduling
and peephole optimizations.< / li >
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< li > < b > < a name = "codemission" > Code Emission< / a > < / b > - The final stage actually
puts out the code for the current function, either in the target assembler
format or in machine code.< / li >
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< / ol >
< p >
The code generator is based on the assumption that the instruction selector will
use an optimal pattern matching selector to create high-quality sequences of
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native instructions. Alternative code generator designs based on pattern
expansion and
aggressive iterative peephole optimization are much slower. This design
permits efficient compilation (important for JIT environments) and
aggressive optimization (used when generating code offline) by allowing
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components of varying levels of sophistication to be used for any step of
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compilation.< / p >
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< p >
In addition to these stages, target implementations can insert arbitrary
target-specific passes into the flow. For example, the X86 target uses a
special pass to handle the 80x87 floating point stack architecture. Other
targets with unusual requirements can be supported with custom passes as needed.
< / p >
< / div >
<!-- ======================================================================= -->
< div class = "doc_subsection" >
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< a name = "tablegen" > Using TableGen for target description< / a >
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< / div >
< div class = "doc_text" >
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< p > The target description classes require a detailed description of the target
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architecture. These target descriptions often have a large amount of common
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information (e.g., an < tt > add< / tt > instruction is almost identical to a
< tt > sub< / tt > instruction).
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In order to allow the maximum amount of commonality to be factored out, the LLVM
code generator uses the < a href = "TableGenFundamentals.html" > TableGen< / a > tool to
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describe big chunks of the target machine, which allows the use of
domain-specific and target-specific abstractions to reduce the amount of
repetition.
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< / p >
< / div >
<!-- *********************************************************************** -->
< div class = "doc_section" >
< a name = "targetdesc" > Target description classes< / a >
< / div >
<!-- *********************************************************************** -->
< div class = "doc_text" >
< p > The LLVM target description classes (which are located in the
< tt > include/llvm/Target< / tt > directory) provide an abstract description of the
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target machine; independent of any particular client. These classes are
designed to capture the < i > abstract< / i > properties of the target (such as the
instructions and registers it has), and do not incorporate any particular pieces
of code generation algorithms. These interfaces do not take interference graphs
as inputs or other algorithm-specific data structures.< / p >
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< p > All of the target description classes (except the < tt > < a
href="#targetdata">TargetData< / a > < / tt > class) are designed to be subclassed by
the concrete target implementation, and have virtual methods implemented. To
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get to these implementations, the < tt > < a
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href="#targetmachine">TargetMachine< / a > < / tt > class provides accessors that
should be implemented by the target.< / p >
< / div >
<!-- ======================================================================= -->
< div class = "doc_subsection" >
< a name = "targetmachine" > The < tt > TargetMachine< / tt > class< / a >
< / div >
< div class = "doc_text" >
< p > The < tt > TargetMachine< / tt > class provides virtual methods that are used to
access the target-specific implementations of the various target description
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classes via the < tt > get*Info< / tt > methods (< tt > getInstrInfo< / tt > ,
< tt > getRegisterInfo< / tt > , < tt > getFrameInfo< / tt > , etc.). This class is
designed to be specialized by
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a concrete target implementation (e.g., < tt > X86TargetMachine< / tt > ) which
implements the various virtual methods. The only required target description
class is the < a href = "#targetdata" > < tt > TargetData< / tt > < / a > class, but if the
code generator components are to be used, the other interfaces should be
implemented as well.< / p >
< / div >
<!-- ======================================================================= -->
< div class = "doc_subsection" >
< a name = "targetdata" > The < tt > TargetData< / tt > class< / a >
< / div >
< div class = "doc_text" >
< p > The < tt > TargetData< / tt > class is the only required target description class,
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and it is the only class that is not extensible. You cannot derived a new
class from it. < tt > TargetData< / tt > specifies information about how the target
lays out memory for structures, the alignment requirements for various data
types, the size of pointers in the target, and whether the target is
little-endian or big-endian.< / p >
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< / div >
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<!-- ======================================================================= -->
< div class = "doc_subsection" >
< a name = "targetlowering" > The < tt > TargetLowering< / tt > class< / a >
< / div >
< div class = "doc_text" >
< p > The < tt > TargetLowering< / tt > class is used by SelectionDAG based instruction
selectors primarily to describe how LLVM code should be lowered to SelectionDAG
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operations. Among other things, this class indicates:
< ul > < li > an initial register class to use for various ValueTypes,< / li >
< li > which operations are natively supported by the target machine,< / li >
< li > the return type of setcc operations, and< / li >
< li > the type to use for shift amounts, etc< / li > .
< / ol > < / p >
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< / div >
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<!-- ======================================================================= -->
< div class = "doc_subsection" >
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< a name = "mregisterinfo" > The < tt > MRegisterInfo< / tt > class< / a >
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< / div >
< div class = "doc_text" >
< p > The < tt > MRegisterInfo< / tt > class (which will eventually be renamed to
< tt > TargetRegisterInfo< / tt > ) is used to describe the register file of the
target and any interactions between the registers.< / p >
< p > Registers in the code generator are represented in the code generator by
unsigned numbers. Physical registers (those that actually exist in the target
description) are unique small numbers, and virtual registers are generally
large.< / p >
< p > Each register in the processor description has an associated
< tt > MRegisterDesc< / tt > entry, which provides a textual name for the register
(used for assembly output and debugging dumps), a set of aliases (used to
indicate that one register overlaps with another), and some flag bits.
< / p >
< p > In addition to the per-register description, the < tt > MRegisterInfo< / tt > class
exposes a set of processor specific register classes (instances of the
< tt > TargetRegisterClass< / tt > class). Each register class contains sets of
registers that have the same properties (for example, they are all 32-bit
integer registers). Each SSA virtual register created by the instruction
selector has an associated register class. When the register allocator runs, it
replaces virtual registers with a physical register in the set.< / p >
< p >
The target-specific implementations of these classes is auto-generated from a < a
href="TableGenFundamentals.html">TableGen< / a > description of the register file.
< / p >
< / div >
<!-- ======================================================================= -->
< div class = "doc_subsection" >
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< a name = "targetinstrinfo" > The < tt > TargetInstrInfo< / tt > class< / a >
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< / div >
<!-- ======================================================================= -->
< div class = "doc_subsection" >
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< a name = "targetframeinfo" > The < tt > TargetFrameInfo< / tt > class< / a >
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< / div >
<!-- ======================================================================= -->
< div class = "doc_subsection" >
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< a name = "targetjitinfo" > The < tt > TargetJITInfo< / tt > class< / a >
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< / div >
<!-- *********************************************************************** -->
< div class = "doc_section" >
< a name = "codegendesc" > Machine code description classes< / a >
< / div >
<!-- *********************************************************************** -->
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< div class = "doc_text" >
< p >
At the high-level, LLVM code is translated to a machine specific representation
formed out of MachineFunction, MachineBasicBlock, and < a
href="#machineinstr">< tt > MachineInstr< / tt > < / a > instances
(defined in include/llvm/CodeGen). This representation is completely target
agnostic, representing instructions in their most abstract form: an opcode and a
series of operands. This representation is designed to support both SSA
representation for machine code, as well as a register allocated, non-SSA form.
< / p >
< / div >
<!-- ======================================================================= -->
< div class = "doc_subsection" >
< a name = "machineinstr" > The < tt > MachineInstr< / tt > class< / a >
< / div >
< div class = "doc_text" >
< p > Target machine instructions are represented as instances of the
< tt > MachineInstr< / tt > class. This class is an extremely abstract way of
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representing machine instructions. In particular, it only keeps track of
an opcode number and a set of operands.< / p >
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< p > The opcode number is a simple unsigned number that only has meaning to a
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specific backend. All of the instructions for a target should be defined in
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the < tt > *InstrInfo.td< / tt > file for the target. The opcode enum values
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are auto-generated from this description. The < tt > MachineInstr< / tt > class does
not have any information about how to interpret the instruction (i.e., what the
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semantics of the instruction are): for that you must refer to the
< tt > < a href = "#targetinstrinfo" > TargetInstrInfo< / a > < / tt > class.< / p >
< p > The operands of a machine instruction can be of several different types:
they can be a register reference, constant integer, basic block reference, etc.
In addition, a machine operand should be marked as a def or a use of the value
(though only registers are allowed to be defs).< / p >
< p > By convention, the LLVM code generator orders instruction operands so that
all register definitions come before the register uses, even on architectures
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that are normally printed in other orders. For example, the SPARC add
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instruction: "< tt > add %i1, %i2, %i3< / tt > " adds the "%i1", and "%i2" registers
and stores the result into the "%i3" register. In the LLVM code generator,
the operands should be stored as "< tt > %i3, %i1, %i2< / tt > ": with the destination
first.< / p >
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< p > Keeping destination (definition) operands at the beginning of the operand
list has several advantages. In particular, the debugging printer will print
the instruction like this:< / p >
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< pre >
%r3 = add %i1, %i2
< / pre >
< p > If the first operand is a def, and it is also easier to < a
href="#buildmi">create instructions< / a > whose only def is the first
operand.< / p >
< / div >
<!-- _______________________________________________________________________ -->
< div class = "doc_subsubsection" >
< a name = "buildmi" > Using the < tt > MachineInstrBuilder.h< / tt > functions< / a >
< / div >
< div class = "doc_text" >
< p > Machine instructions are created by using the < tt > BuildMI< / tt > functions,
located in the < tt > include/llvm/CodeGen/MachineInstrBuilder.h< / tt > file. The
< tt > BuildMI< / tt > functions make it easy to build arbitrary machine
instructions. Usage of the < tt > BuildMI< / tt > functions look like this:
< / p >
< pre >
// Create a 'DestReg = mov 42' (rendered in X86 assembly as 'mov DestReg, 42')
// instruction. The '1' specifies how many operands will be added.
MachineInstr *MI = BuildMI(X86::MOV32ri, 1, DestReg).addImm(42);
// Create the same instr, but insert it at the end of a basic block.
MachineBasicBlock & MBB = ...
BuildMI(MBB, X86::MOV32ri, 1, DestReg).addImm(42);
// Create the same instr, but insert it before a specified iterator point.
MachineBasicBlock::iterator MBBI = ...
BuildMI(MBB, MBBI, X86::MOV32ri, 1, DestReg).addImm(42);
// Create a 'cmp Reg, 0' instruction, no destination reg.
MI = BuildMI(X86::CMP32ri, 2).addReg(Reg).addImm(0);
// Create an 'sahf' instruction which takes no operands and stores nothing.
MI = BuildMI(X86::SAHF, 0);
// Create a self looping branch instruction.
BuildMI(MBB, X86::JNE, 1).addMBB(& MBB);
< / pre >
< p >
The key thing to remember with the < tt > BuildMI< / tt > functions is that you have
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to specify the number of operands that the machine instruction will take. This
allows for efficient memory allocation. You also need to specify if operands
default to be uses of values, not definitions. If you need to add a definition
operand (other than the optional destination register), you must explicitly
mark it as such.
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< / p >
< / div >
<!-- _______________________________________________________________________ -->
< div class = "doc_subsubsection" >
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< a name = "fixedregs" > Fixed (preassigned) registers< / a >
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< / div >
< div class = "doc_text" >
< p > One important issue that the code generator needs to be aware of is the
presence of fixed registers. In particular, there are often places in the
instruction stream where the register allocator < em > must< / em > arrange for a
particular value to be in a particular register. This can occur due to
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limitations of the instruction set (e.g., the X86 can only do a 32-bit divide
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with the < tt > EAX< / tt > /< tt > EDX< / tt > registers), or external factors like calling
conventions. In any case, the instruction selector should emit code that
copies a virtual register into or out of a physical register when needed.< / p >
< p > For example, consider this simple LLVM example:< / p >
< pre >
int %test(int %X, int %Y) {
%Z = div int %X, %Y
ret int %Z
}
< / pre >
< p > The X86 instruction selector produces this machine code for the div
and ret (use
"< tt > llc X.bc -march=x86 -print-machineinstrs< / tt > " to get this):< / p >
< pre >
;; Start of div
%EAX = mov %reg1024 ;; Copy X (in reg1024) into EAX
%reg1027 = sar %reg1024, 31
%EDX = mov %reg1027 ;; Sign extend X into EDX
idiv %reg1025 ;; Divide by Y (in reg1025)
%reg1026 = mov %EAX ;; Read the result (Z) out of EAX
;; Start of ret
%EAX = mov %reg1026 ;; 32-bit return value goes in EAX
ret
< / pre >
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< p > By the end of code generation, the register allocator has coalesced
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the registers and deleted the resultant identity moves, producing the
following code:< / p >
< pre >
;; X is in EAX, Y is in ECX
mov %EAX, %EDX
sar %EDX, 31
idiv %ECX
ret
< / pre >
< p > This approach is extremely general (if it can handle the X86 architecture,
it can handle anything!) and allows all of the target specific
knowledge about the instruction stream to be isolated in the instruction
selector. Note that physical registers should have a short lifetime for good
code generation, and all physical registers are assumed dead on entry and
exit of basic blocks (before register allocation). Thus if you need a value
to be live across basic block boundaries, it < em > must< / em > live in a virtual
register.< / p >
< / div >
<!-- _______________________________________________________________________ -->
< div class = "doc_subsubsection" >
< a name = "ssa" > Machine code SSA form< / a >
< / div >
< div class = "doc_text" >
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< p > < tt > MachineInstr< / tt > 's are initially selected in SSA-form, and
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are maintained in SSA-form until register allocation happens. For the most
part, this is trivially simple since LLVM is already in SSA form: LLVM PHI nodes
become machine code PHI nodes, and virtual registers are only allowed to have a
single definition.< / p >
< p > After register allocation, machine code is no longer in SSA-form, as there
are no virtual registers left in the code.< / p >
< / div >
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<!-- *********************************************************************** -->
< div class = "doc_section" >
< a name = "codegenalgs" > Target-independent code generation algorithms< / a >
< / div >
<!-- *********************************************************************** -->
< div class = "doc_text" >
< p > This section documents the phases described in the < a
href="high-level-design">high-level design of the code generator< / a > . It
explains how they work and some of the rationale behind their design.< / p >
< / div >
<!-- ======================================================================= -->
< div class = "doc_subsection" >
< a name = "instselect" > Instruction Selection< / a >
< / div >
< div class = "doc_text" >
< p >
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Instruction Selection is the process of translating LLVM code presented to the
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code generator into target-specific machine instructions. There are several
well-known ways to do this in the literature. In LLVM there are two main forms:
the old-style 'simple' instruction selector (which effectively peephole selects
each LLVM instruction into a series of machine instructions), and the new
SelectionDAG based instruction selector.
< / p >
< p > The 'simple' instruction selectors are tedious to write, require a lot of
boiler plate code, and are difficult to get correct. Additionally, any
optimizations written for a simple instruction selector cannot be used by other
targets. For this reason, LLVM is moving to a new SelectionDAG based
instruction selector, which is described in this section. If you are starting a
new port, we recommend that you write the instruction selector using the
SelectionDAG infrastructure.< / p >
< p > In time, most of the target-specific code for instruction selection will be
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auto-generated from the target description (< tt > *.td< / tt > ) files. For now,
however, the < a href = "#selectiondag_select" > Select Phase< / a > must still be
written by hand.< / p >
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< / div >
<!-- _______________________________________________________________________ -->
< div class = "doc_subsubsection" >
< a name = "selectiondag_intro" > Introduction to SelectionDAGs< / a >
< / div >
< div class = "doc_text" >
< p >
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The SelectionDAG provides an abstraction for code representation in a way that
is amenable to instruction selection using automatic techniques
(e.g. dynamic-programming based optimal pattern matching selectors), It is also
well suited to other phases of code generation; in particular, instruction scheduling. Additionally, the SelectionDAG provides a host representation where a
large variety of very-low-level (but target-independent)
< a href = "#selectiondag_optimize" > optimizations< / a > may be
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performed: ones which require extensive information about the instructions
efficiently supported by the target.
< / p >
< p >
The SelectionDAG is a Directed-Acyclic-Graph whose nodes are instances of the
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< tt > SDNode< / tt > class. The primary payload of the < tt > SDNode< / tt > is its
operation code (Opcode) that indicates what operation the node performs.
The various operation node types are described at the top of the
< tt > include/llvm/CodeGen/SelectionDAGNodes.h< / tt > file. Depending on the
operation, nodes may contain additional information (e.g. the condition code
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for a SETCC node) contained in a derived class.< / p >
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< p > Although most operations define a single value, each node in the graph may
define multiple values. For example, a combined div/rem operation will define
both the dividend and the remainder. Many other situations require multiple
values as well. Each node also has some number of operands, which are edges
to the node defining the used value. Because nodes may define multiple values,
edges are represented by instances of the < tt > SDOperand< / tt > class, which is
a < SDNode, unsigned> pair, indicating the node and result
value being used, respectively. Each value produced by an SDNode has an
associated MVT::ValueType, indicating what type the value is.
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< / p >
< p >
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SelectionDAGs contain two different kinds of values: those that represent data
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flow and those that represent control flow dependencies. Data values are simple
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edges with an integer or floating point value type. Control edges are
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represented as "chain" edges which are of type MVT::Other. These edges provide
an ordering between nodes that have side effects (such as
loads/stores/calls/return/etc). All nodes that have side effects should take a
token chain as input and produce a new one as output. By convention, token
chain inputs are always operand #0, and chain results are always the last
value produced by an operation.< / p >
< p >
A SelectionDAG has designated "Entry" and "Root" nodes. The Entry node is
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always a marker node with an Opcode of ISD::EntryToken. The Root node is the
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final side-effecting node in the token chain. For example, in a single basic
block function, this would be the return node.
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< / p >
< p >
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One important concept for SelectionDAGs is the notion of a "legal" vs. "illegal"
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DAG. A legal DAG for a target is one that only uses supported operations and
supported types. On PowerPC, for example, a DAG with any values of i1, i8, i16,
or i64 type would be illegal. The < a href = "#selectiondag_legalize" > legalize< / a >
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phase is responsible for turning an illegal DAG into a legal DAG.
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< / p >
< / div >
<!-- _______________________________________________________________________ -->
< div class = "doc_subsubsection" >
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< a name = "selectiondag_process" > SelectionDAG Instruction Selection Process< / a >
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< / div >
< div class = "doc_text" >
< p >
SelectionDAG-based instruction selection consists of the following steps:
< / p >
< ol >
< li > < a href = "#selectiondag_build" > Build initial DAG< / a > - This stage performs
a simple translation from the input LLVM code to an illegal SelectionDAG.
< / li >
< li > < a href = "#selectiondag_optimize" > Optimize SelectionDAG< / a > - This stage
performs simple optimizations on the SelectionDAG to simplify it and
recognize meta instructions (like rotates and div/rem pairs) for
targets that support these meta operations. This makes the resultant code
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more efficient and the 'select instructions from DAG' phase (below) simpler.
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< / li >
< li > < a href = "#selectiondag_legalize" > Legalize SelectionDAG< / a > - This stage
converts the illegal SelectionDAG to a legal SelectionDAG, by eliminating
unsupported operations and data types.< / li >
< li > < a href = "#selectiondag_optimize" > Optimize SelectionDAG (#2)< / a > - This
second run of the SelectionDAG optimized the newly legalized DAG, to
eliminate inefficiencies introduced by legalization.< / li >
< li > < a href = "#selectiondag_select" > Select instructions from DAG< / a > - Finally,
the target instruction selector matches the DAG operations to target
instructions, emitting them and building the MachineFunction being
compiled.< / li >
< / ol >
< p > After all of these steps are complete, the SelectionDAG is destroyed and the
rest of the code generation passes are run.< / p >
< / div >
<!-- _______________________________________________________________________ -->
< div class = "doc_subsubsection" >
< a name = "selectiondag_build" > Initial SelectionDAG Construction< / a >
< / div >
< div class = "doc_text" >
< p >
The initial SelectionDAG is naively peephole expanded from the LLVM input by
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the < tt > SelectionDAGLowering< / tt > class in the SelectionDAGISel.cpp file. The
intent of this pass is to expose as much low-level, target-specific details
to the SelectionDAG as possible. This pass is mostly hard-coded (e.g. an LLVM
add turns into an SDNode add while a geteelementptr is expanded into the obvious
arithmetic). This pass requires target-specific hooks to lower calls and
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returns, varargs, etc. For these features, the TargetLowering interface is
used.
< / p >
< / div >
<!-- _______________________________________________________________________ -->
< div class = "doc_subsubsection" >
< a name = "selectiondag_legalize" > SelectionDAG Legalize Phase< / a >
< / div >
< div class = "doc_text" >
< p > The Legalize phase is in charge of converting a DAG to only use the types and
operations that are natively supported by the target. This involves two major
tasks:< / p >
< ol >
< li > < p > Convert values of unsupported types to values of supported types.< / p >
< p > There are two main ways of doing this: promoting a small type to a larger
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type (e.g. f32 -> f64, or i16 -> i32), and breaking up large
integer types
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to smaller ones (e.g. implementing i64 with i32 operations where
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possible). Type conversions can insert sign and zero extensions as
needed to make sure that the final code has the same behavior as the
input.< / p >
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< / li >
< li > < p > Eliminate operations that are not supported by the target in a supported
type.< / p >
< p > Targets often have wierd constraints, such as not supporting every
operation on every supported datatype (e.g. X86 does not support byte
conditional moves). Legalize takes care of either open-coding another
sequence of operations to emulate the operation (this is known as
expansion), promoting to a larger type that supports the operation
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(promotion), or using a target-specific hook to implement the
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legalization.< / p >
< / li >
< / ol >
< p >
Instead of using a Legalize pass, we could require that every target-specific
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< a href = "#selectiondag_optimize" > selector< / a > supports and expands every
operator and type even if they are not supported and may require many
instructions to implement (in fact, this is the approach taken by the
"simple" selectors). However, using a Legalize pass allows all of the
cannonicalization patterns to be shared across targets which makes it very
easy to optimize the cannonicalized code because it is still in the form of
a DAG.
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< / p >
< / div >
<!-- _______________________________________________________________________ -->
< div class = "doc_subsubsection" >
< a name = "selectiondag_optimize" > SelectionDAG Optimization Phase< / a >
< / div >
< div class = "doc_text" >
< p >
The SelectionDAG optimization phase is run twice for code generation: once
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immediately after the DAG is built and once after legalization. The first run
of the pass allows the initial code to be cleaned up (e.g. performing
optimizations that depend on knowing that the operators have restricted type
inputs). The second run of the pass cleans up the messy code generated by the
Legalize pass, allowing Legalize to be very simple since it can ignore many
special cases.
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< / p >
< p >
One important class of optimizations that this pass will do in the future is
optimizing inserted sign and zero extension instructions. Here are some good
papers on the subject:< / p >
< p >
"< a href = "http://www.eecs.harvard.edu/~nr/pubs/widen-abstract.html" > Widening
integer arithmetic< / a > "< br >
Kevin Redwine and Norman Ramsey< br >
International Conference on Compiler Construction (CC) 2004
< / p >
< p >
"< a href = "http://portal.acm.org/citation.cfm?doid=512529.512552" > Effective
sign extension elimination< / a > "< br >
Motohiro Kawahito, Hideaki Komatsu, and Toshio Nakatani< br >
Proceedings of the ACM SIGPLAN 2002 Conference on Programming Language Design
and Implementation.
< / p >
< / div >
<!-- _______________________________________________________________________ -->
< div class = "doc_subsubsection" >
< a name = "selectiondag_select" > SelectionDAG Select Phase< / a >
< / div >
< div class = "doc_text" >
< p > The Select phase is the bulk of the target-specific code for instruction
selection. This phase takes a legal SelectionDAG as input, and does simple
pattern matching on the DAG to generate code. In time, the Select phase will
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be automatically generated from the target's InstrInfo.td file, which is why we
want to make the Select phase as simple and mechanical as possible.< / p >
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< / div >
<!-- _______________________________________________________________________ -->
< div class = "doc_subsubsection" >
< a name = "selectiondag_future" > Future directions for the SelectionDAG< / a >
< / div >
< div class = "doc_text" >
< ol >
< li > Optional whole-function selection.< / li >
< li > Select is a graph translation phase.< / li >
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< li > Place the machine instructions resulting from Select according to register
pressure or a schedule.< / li >
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< li > DAG Scheduling.< / li >
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< li > Auto-generate the Select phase from the target description (*.td) files.
< / li >
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< / ol >
< / div >
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<!-- ======================================================================= -->
< div class = "doc_subsection" >
< a name = "ssamco" > SSA-based Machine Code Optimizations< / a >
< / div >
< div class = "doc_text" > < p > To Be Written< / p > < / div >
<!-- ======================================================================= -->
< div class = "doc_subsection" >
< a name = "regalloc" > Register Allocation< / a >
< / div >
< div class = "doc_text" > < p > To Be Written< / p > < / div >
<!-- ======================================================================= -->
< div class = "doc_subsection" >
< a name = "proepicode" > Prolog/Epilog Code Insertion< / a >
< / div >
< div class = "doc_text" > < p > To Be Written< / p > < / div >
<!-- ======================================================================= -->
< div class = "doc_subsection" >
< a name = "latemco" > Late Machine Code Optimizations< / a >
< / div >
< div class = "doc_text" > < p > To Be Written< / p > < / div >
<!-- ======================================================================= -->
< div class = "doc_subsection" >
< a name = "codemission" > Code Emission< / a >
< / div >
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<!-- *********************************************************************** -->
< div class = "doc_section" >
< a name = "targetimpls" > Target description implementations< / a >
< / div >
<!-- *********************************************************************** -->
< div class = "doc_text" >
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< p > This section of the document explains features or design decisions that
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are specific to the code generator for a particular target.< / p >
< / div >
<!-- ======================================================================= -->
< div class = "doc_subsection" >
< a name = "x86" > The X86 backend< / a >
< / div >
< div class = "doc_text" >
< p >
The X86 code generator lives in the < tt > lib/Target/X86< / tt > directory. This
code generator currently targets a generic P6-like processor. As such, it
produces a few P6-and-above instructions (like conditional moves), but it does
not make use of newer features like MMX or SSE. In the future, the X86 backend
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will have sub-target support added for specific processor families and
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implementations.< / p >
< / div >
<!-- _______________________________________________________________________ -->
< div class = "doc_subsubsection" >
< a name = "x86_memory" > Representing X86 addressing modes in MachineInstrs< / a >
< / div >
< div class = "doc_text" >
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< p > The x86 has a very flexible way of accessing memory. It is capable of
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forming memory addresses of the following expression directly in integer
instructions (which use ModR/M addressing):< / p >
< pre >
Base+[1,2,4,8]*IndexReg+Disp32
< / pre >
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< p > In order to represent this, LLVM tracks no less than 4 operands for each
memory operand of this form. This means that the "load" form of 'mov' has the
following < tt > MachineOperand< / tt > s in this order:< / p >
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< pre >
Index: 0 | 1 2 3 4
Meaning: DestReg, | BaseReg, Scale, IndexReg, Displacement
OperandTy: VirtReg, | VirtReg, UnsImm, VirtReg, SignExtImm
< / pre >
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< p > Stores, and all other instructions, treat the four memory operands in the
same way, in the same order.< / p >
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< / div >
<!-- _______________________________________________________________________ -->
< div class = "doc_subsubsection" >
< a name = "x86_names" > Instruction naming< / a >
< / div >
< div class = "doc_text" >
< p >
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An instruction name consists of the base name, a default operand size, and a
a character per operand with an optional special size. For example:< / p >
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< p >
< tt > ADD8rr< / tt > -> add, 8-bit register, 8-bit register< br >
< tt > IMUL16rmi< / tt > -> imul, 16-bit register, 16-bit memory, 16-bit immediate< br >
< tt > IMUL16rmi8< / tt > -> imul, 16-bit register, 16-bit memory, 8-bit immediate< br >
< tt > MOVSX32rm16< / tt > -> movsx, 32-bit register, 16-bit memory
< / p >
< / div >
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<!-- *********************************************************************** -->
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