2010-10-14 23:49:52 +00:00
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//===---- LiveRangeEdit.h - Basic tools for split and spill -----*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// The LiveRangeEdit class represents changes done to a virtual register when it
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// is spilled or split.
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//
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// The parent register is never changed. Instead, a number of new virtual
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// registers are created and added to the newRegs vector.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_LIVERANGEEDIT_H
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#define LLVM_CODEGEN_LIVERANGEEDIT_H
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#include "llvm/CodeGen/LiveInterval.h"
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namespace llvm {
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class LiveIntervals;
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class MachineRegisterInfo;
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class VirtRegMap;
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class LiveRangeEdit {
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LiveInterval &parent_;
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SmallVectorImpl<LiveInterval*> &newRegs_;
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const SmallVectorImpl<LiveInterval*> &uselessRegs_;
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/// firstNew_ - Index of the first register added to newRegs_.
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const unsigned firstNew_;
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public:
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/// Create a LiveRangeEdit for breaking down parent into smaller pieces.
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/// @param parent The register being spilled or split.
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/// @param newRegs List to receive any new registers created. This needn't be
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/// empty initially, any existing registers are ignored.
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/// @param uselessRegs List of registers that can't be used when
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/// rematerializing values because they are about to be removed.
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LiveRangeEdit(LiveInterval &parent,
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SmallVectorImpl<LiveInterval*> &newRegs,
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const SmallVectorImpl<LiveInterval*> &uselessRegs)
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: parent_(parent), newRegs_(newRegs), uselessRegs_(uselessRegs),
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firstNew_(newRegs.size()) {}
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LiveInterval &getParent() const { return parent_; }
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unsigned getReg() const { return parent_.reg; }
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/// Iterator for accessing the new registers added by this edit.
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typedef SmallVectorImpl<LiveInterval*>::const_iterator iterator;
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iterator begin() const { return newRegs_.begin()+firstNew_; }
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iterator end() const { return newRegs_.end(); }
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2010-10-15 00:16:55 +00:00
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/// assignStackSlot - Ensure a stack slot is assigned to parent.
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/// @return the assigned stack slot number.
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int assignStackSlot(VirtRegMap&);
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/// create - Create a new register with the same class and stack slot as
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/// parent.
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2010-10-14 23:49:52 +00:00
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LiveInterval &create(MachineRegisterInfo&, LiveIntervals&, VirtRegMap&);
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/// allUsesAvailableAt - Return true if all registers used by OrigMI at
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/// OrigIdx are also available with the same value at UseIdx.
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bool allUsesAvailableAt(const MachineInstr *OrigMI, SlotIndex OrigIdx,
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SlotIndex UseIdx, LiveIntervals &lis);
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};
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}
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#endif
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