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Add support for the %H output modifier.

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Patch by Weiming Zhao.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161768 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eric Christopher 2012-08-13 18:18:52 +00:00
parent 365a1d48d8
commit 001d219b97
2 changed files with 24 additions and 2 deletions
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17
lib/Target/ARM/ARMAsmPrinter.cpp
View File

@ -529,10 +529,23 @@ bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
return false;
}
// These modifiers are not yet supported.
// This modifier is not yet supported.
case 'h': // A range of VFP/NEON registers suitable for VLD1/VST1.
case 'H': // The highest-numbered register of a pair.
return true;
case 'H': // The highest-numbered register of a pair.
const MachineOperand &MO = MI->getOperand(OpNum);
if (!MO.isReg())
return true;
const TargetRegisterClass &RC = ARM::GPRRegClass;
const MachineFunction &MF = *MI->getParent()->getParent();
const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo();
unsigned RegIdx = TRI->getEncodingValue(MO.getReg());
RegIdx |= 1; //The odd register is also the higher-numbered one of a pair.
unsigned Reg = RC.getRegister(RegIdx);
O << ARMInstPrinter::getRegisterName(Reg);
return false;
}
}

9
test/CodeGen/ARM/arm-modifier.ll
View File

@ -57,3 +57,12 @@ store i64 %0, i64* @f3_var, align 4
store i64 %1, i64* @f3_var, align 4
ret void
}
define i64 @f4(i64* %val) nounwind {
entry:
;CHECK: f4
;CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], {{r[0-9]?[13579]}}, [r0]
;CHECK: mov r0, [[REG1]]
%0 = tail call i64 asm sideeffect "ldrexd $0, ${0:H}, [$1]", "=&r,r,*Qo"(i64* %val, i64* %val) nounwind
ret i64 %0
}