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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28311 91177308-0d34-0410-b5e6-96231b3b80d8
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		| @@ -1307,7 +1307,7 @@ static SDOperand GeneratePerfectShuffle(unsigned PFEntry, SDOperand LHS, | |||||||
|   unsigned RHSID = (PFEntry >>  0) & ((1 << 13)-1); |   unsigned RHSID = (PFEntry >>  0) & ((1 << 13)-1); | ||||||
|    |    | ||||||
|   enum { |   enum { | ||||||
|     OP_COPY = 0,   // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3> |     OP_COPY = 0,  // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3> | ||||||
|     OP_VMRGHW, |     OP_VMRGHW, | ||||||
|     OP_VMRGLW, |     OP_VMRGLW, | ||||||
|     OP_VSPLTISW0, |     OP_VSPLTISW0, | ||||||
| @@ -1978,9 +1978,9 @@ PPCTargetLowering::LowerCallTo(SDOperand Chain, | |||||||
|         // free GPRs, then we can pass both halves of the i64 in registers. |         // free GPRs, then we can pass both halves of the i64 in registers. | ||||||
|         if (GPR_remaining > 0) { |         if (GPR_remaining > 0) { | ||||||
|           SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, |           SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, | ||||||
|                                      Args[i].first, DAG.getConstant(1, MVT::i32)); |                                    Args[i].first, DAG.getConstant(1, MVT::i32)); | ||||||
|           SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, |           SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, | ||||||
|                                      Args[i].first, DAG.getConstant(0, MVT::i32)); |                                    Args[i].first, DAG.getConstant(0, MVT::i32)); | ||||||
|           args_to_use.push_back(Hi); |           args_to_use.push_back(Hi); | ||||||
|           --GPR_remaining; |           --GPR_remaining; | ||||||
|           if (GPR_remaining > 0) { |           if (GPR_remaining > 0) { | ||||||
|   | |||||||
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