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Sched itinerary fix: Avoid static initializers.

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This fixes an accidental dependence on static initialization order that I introduced yesterday.

Thank you Lang!!!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158215 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrew Trick
2012-06-08 18:25:47 +00:00
parent 28dd960cd1
commit 0076ad7eeb
2 changed files with 13 additions and 4 deletions
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14
include/llvm/MC/MCInstrItineraries.h
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@@ -111,6 +111,7 @@ struct InstrItineraryProps {
// IssueWidth is the maximum number of instructions that may be scheduled in // IssueWidth is the maximum number of instructions that may be scheduled in
// the same per-cycle group. // the same per-cycle group.
unsigned IssueWidth; unsigned IssueWidth;
static const unsigned DefaultIssueWidth = 1;
// MinLatency is the minimum latency between a register write // MinLatency is the minimum latency between a register write
// followed by a data dependent read. This determines which // followed by a data dependent read. This determines which
@@ -133,12 +134,14 @@ struct InstrItineraryProps {
// Optional InstrItinerary OperandCycles provides expected latency. // Optional InstrItinerary OperandCycles provides expected latency.
// TODO: can't yet specify both min and expected latency per operand. // TODO: can't yet specify both min and expected latency per operand.
int MinLatency; int MinLatency;
static const unsigned DefaultMinLatency = -1;
// LoadLatency is the expected latency of load instructions. // LoadLatency is the expected latency of load instructions.
// //
// If MinLatency >= 0, this may be overriden for individual load opcodes by // If MinLatency >= 0, this may be overriden for individual load opcodes by
// InstrItinerary OperandCycles. // InstrItinerary OperandCycles.
unsigned LoadLatency; unsigned LoadLatency;
static const unsigned DefaultLoadLatency = 4;
// HighLatency is the expected latency of "very high latency" operations. // HighLatency is the expected latency of "very high latency" operations.
// See TargetInstrInfo::isHighLatencyDef(). // See TargetInstrInfo::isHighLatencyDef().
@@ -146,9 +149,16 @@ struct InstrItineraryProps {
// likely to have some impact on scheduling heuristics. // likely to have some impact on scheduling heuristics.
// If MinLatency >= 0, this may be overriden by InstrItinData OperandCycles. // If MinLatency >= 0, this may be overriden by InstrItinData OperandCycles.
unsigned HighLatency; unsigned HighLatency;
static const unsigned DefaultHighLatency = 10;
InstrItineraryProps(): IssueWidth(1), MinLatency(-1), LoadLatency(4), // Default's must be specified as static const literals so that tablegenerated
HighLatency(10) {} // target code can use it in static initializers. The defaults need to be
// initialized in this default ctor because some clients directly instantiate
// InstrItineraryData instead of using a generated itinerary.
InstrItineraryProps(): IssueWidth(DefaultMinLatency),
MinLatency(DefaultMinLatency),
LoadLatency(DefaultLoadLatency),
HighLatency(DefaultHighLatency) {}
InstrItineraryProps(unsigned iw, int ml, unsigned ll, unsigned hl): InstrItineraryProps(unsigned iw, int ml, unsigned ll, unsigned hl):
IssueWidth(iw), MinLatency(ml), LoadLatency(ll), HighLatency(hl) {} IssueWidth(iw), MinLatency(ml), LoadLatency(ll), HighLatency(hl) {}

3
utils/TableGen/SubtargetEmitter.cpp
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@@ -485,7 +485,7 @@ void SubtargetEmitter::EmitItineraryProp(raw_ostream &OS, const Record *R,
if (V >= 0) if (V >= 0)
OS << V << Separator << " // " << Name; OS << V << Separator << " // " << Name;
else else
OS << "DefaultItineraryProps." << Name << Separator; OS << "InstrItineraryProps::Default" << Name << Separator;
OS << '\n'; OS << '\n';
} }
@@ -496,7 +496,6 @@ void SubtargetEmitter::
EmitProcessorData(raw_ostream &OS, EmitProcessorData(raw_ostream &OS,
std::vector<Record*> &ItinClassList, std::vector<Record*> &ItinClassList,
std::vector<std::vector<InstrItinerary> > &ProcList) { std::vector<std::vector<InstrItinerary> > &ProcList) {
OS << "static const llvm::InstrItineraryProps " << "DefaultItineraryProps;";
// Get an iterator for processor itinerary stages // Get an iterator for processor itinerary stages
std::vector<std::vector<InstrItinerary> >::iterator std::vector<std::vector<InstrItinerary> >::iterator