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[mips] Add some comments related to the optimization performed in performSELECTCombine.

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The structure of the code was slightly modified so that the next patch is easier to read/review.

No functional changes.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196496 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matheus Almeida 2013-12-05 11:56:56 +00:00
parent 4faa2b38fb
commit 00877e733f
1 changed files with 20 additions and 7 deletions
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27
lib/Target/Mips/MipsISelLowering.cpp
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@ -535,19 +535,32 @@ static SDValue performSELECTCombine(SDNode *N, SelectionDAG &DAG,
if (!FalseTy.isInteger()) if (!FalseTy.isInteger())
return SDValue(); return SDValue();
ConstantSDNode *CN = dyn_cast<ConstantSDNode>(False); ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(False);
if (!CN || CN->getZExtValue()) // If the RHS (False) is 0, we swap the order of the operands
// of ISD::SELECT (obviously also inverting the condition) so that we can
// take advantage of conditional moves using the $0 register.
// Example:
// return (a != 0) ? x : 0;
// load $reg, x
// movz $reg, $0, a
if (!FalseC)
return SDValue(); return SDValue();
const SDLoc DL(N); const SDLoc DL(N);
ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get();
SDValue True = N->getOperand(1);
SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0), if (!FalseC->getZExtValue()) {
SetCC.getOperand(1), ISD::getSetCCInverse(CC, true)); ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get();
SDValue True = N->getOperand(1);
return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True); SetCC = DAG.getSetCC(DL, SetCC.getValueType(), SetCC.getOperand(0),
SetCC.getOperand(1), ISD::getSetCCInverse(CC, true));
return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True);
}
// Couldn't optimize.
return SDValue();
} }
static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG, static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG,