mirror of
https://github.com/c64scene-ar/llvm-6502.git
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Revert r141932, r141936 and r141937.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141959 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka
parent
312b7c950a
commit
008b58c4ae
@ -12,7 +12,6 @@ add_llvm_target(MipsCodeGen
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MipsAsmPrinter.cpp
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MipsCodeEmitter.cpp
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MipsDelaySlotFiller.cpp
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MipsELFWriterInfo.cpp
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MipsEmitGPRestore.cpp
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MipsExpandPseudo.cpp
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MipsJITInfo.cpp
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@ -1,215 +0,0 @@
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//===-- MipsELFWriterInfo.cpp - ELF Writer Info for the Mips backend ------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements ELF writer information for the Mips backend.
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//
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//===----------------------------------------------------------------------===//
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#include "MipsELFWriterInfo.h"
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#include "MipsRelocations.h"
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#include "llvm/Function.h"
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#include "llvm/Support/ELF.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Target/TargetData.h"
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#include "llvm/Target/TargetMachine.h"
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using namespace llvm;
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//===----------------------------------------------------------------------===//
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// Implementation of the MipsELFWriterInfo class
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//===----------------------------------------------------------------------===//
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MipsELFWriterInfo::MipsELFWriterInfo(bool is64Bit_, bool isLittleEndian_)
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: TargetELFWriterInfo(is64Bit_, isLittleEndian_) {
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EMachine = EM_MIPS;
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}
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MipsELFWriterInfo::~MipsELFWriterInfo() {}
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unsigned MipsELFWriterInfo::getRelocationType(unsigned MachineRelTy) const {
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if (is64Bit) {
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switch(MachineRelTy) {
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default:
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llvm_unreachable("unknown Mips_64 machine relocation type");
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}
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} else {
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switch(MachineRelTy) {
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case Mips::reloc_mips_pcrel:
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return ELF::R_MIPS_PC16;
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case Mips::reloc_mips_hi:
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return ELF::R_MIPS_HI16;
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case Mips::reloc_mips_lo:
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return ELF::R_MIPS_LO16;
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case Mips::reloc_mips_j_jal:
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return ELF::R_MIPS_26;
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case Mips::reloc_mips_16:
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return ELF::R_MIPS_16;
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case Mips::reloc_mips_32:
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return ELF::R_MIPS_32;
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case Mips::reloc_mips_rel32:
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return ELF::R_MIPS_REL32;
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case Mips::reloc_mips_gprel16:
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return ELF::R_MIPS_GPREL16;
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case Mips::reloc_mips_literal:
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return ELF::R_MIPS_LITERAL;
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case Mips::reloc_mips_got16:
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return ELF::R_MIPS_GOT16;
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case Mips::reloc_mips_call16:
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return ELF::R_MIPS_CALL16;
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case Mips::reloc_mips_gprel32:
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return ELF::R_MIPS_GPREL32;
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case Mips::reloc_mips_shift5:
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return ELF::R_MIPS_SHIFT5;
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case Mips::reloc_mips_shift6:
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return ELF::R_MIPS_SHIFT6;
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case Mips::reloc_mips_64:
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return ELF::R_MIPS_64;
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case Mips::reloc_mips_tlsgd:
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return ELF::R_MIPS_TLS_GD;
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case Mips::reloc_mips_gottprel:
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return ELF::R_MIPS_TLS_GOTTPREL;
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case Mips::reloc_mips_tprel_hi:
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return ELF::R_MIPS_TLS_TPREL_HI16;
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case Mips::reloc_mips_tprel_lo:
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return ELF::R_MIPS_TLS_TPREL_LO16;
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case Mips::reloc_mips_branch_pcrel:
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return ELF::R_MIPS_PC16;
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default:
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llvm_unreachable("unknown Mips machine relocation type");
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}
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}
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return 0;
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}
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long int MipsELFWriterInfo::getDefaultAddendForRelTy(unsigned RelTy,
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long int Modifier) const {
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if (is64Bit) {
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switch(RelTy) {
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default:
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llvm_unreachable("unknown Mips_64 relocation type");
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}
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} else {
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switch(RelTy) {
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case ELF::R_MIPS_PC16: return Modifier - 4;
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default:
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llvm_unreachable("unknown Mips relocation type");
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}
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}
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return 0;
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}
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unsigned MipsELFWriterInfo::getRelocationTySize(unsigned RelTy) const {
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if (is64Bit) {
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switch(RelTy) {
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case ELF::R_MIPS_PC16:
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case ELF::R_MIPS_HI16:
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case ELF::R_MIPS_LO16:
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case ELF::R_MIPS_26:
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case ELF::R_MIPS_16:
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case ELF::R_MIPS_32:
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case ELF::R_MIPS_REL32:
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case ELF::R_MIPS_GPREL16:
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case ELF::R_MIPS_LITERAL:
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case ELF::R_MIPS_GOT16:
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case ELF::R_MIPS_CALL16:
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case ELF::R_MIPS_GPREL32:
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case ELF::R_MIPS_SHIFT5:
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case ELF::R_MIPS_SHIFT6:
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return 32;
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case ELF::R_MIPS_64:
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return 64;
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default:
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llvm_unreachable("unknown Mips_64 relocation type");
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}
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} else {
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switch(RelTy) {
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case ELF::R_MIPS_PC16:
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case ELF::R_MIPS_HI16:
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case ELF::R_MIPS_LO16:
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case ELF::R_MIPS_26:
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case ELF::R_MIPS_16:
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case ELF::R_MIPS_32:
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case ELF::R_MIPS_REL32:
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case ELF::R_MIPS_GPREL16:
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case ELF::R_MIPS_LITERAL:
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case ELF::R_MIPS_GOT16:
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case ELF::R_MIPS_CALL16:
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case ELF::R_MIPS_GPREL32:
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case ELF::R_MIPS_SHIFT5:
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case ELF::R_MIPS_SHIFT6:
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return 32;
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default:
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llvm_unreachable("unknown Mips relocation type");
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}
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}
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return 0;
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}
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bool MipsELFWriterInfo::isPCRelativeRel(unsigned RelTy) const {
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if (is64Bit) {
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switch(RelTy) {
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case ELF::R_MIPS_PC16:
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return true;
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case ELF::R_MIPS_HI16:
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case ELF::R_MIPS_LO16:
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case ELF::R_MIPS_26:
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case ELF::R_MIPS_16:
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case ELF::R_MIPS_32:
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case ELF::R_MIPS_REL32:
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case ELF::R_MIPS_GPREL16:
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case ELF::R_MIPS_LITERAL:
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case ELF::R_MIPS_GOT16:
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case ELF::R_MIPS_CALL16:
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case ELF::R_MIPS_GPREL32:
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case ELF::R_MIPS_SHIFT5:
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case ELF::R_MIPS_SHIFT6:
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case ELF::R_MIPS_64:
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return false;
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default:
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llvm_unreachable("unknown Mips_64 relocation type");
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}
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} else {
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switch(RelTy) {
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case ELF::R_MIPS_PC16:
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return true;
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case ELF::R_MIPS_HI16:
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case ELF::R_MIPS_LO16:
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case ELF::R_MIPS_26:
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case ELF::R_MIPS_16:
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case ELF::R_MIPS_32:
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case ELF::R_MIPS_REL32:
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case ELF::R_MIPS_GPREL16:
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case ELF::R_MIPS_LITERAL:
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case ELF::R_MIPS_GOT16:
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case ELF::R_MIPS_CALL16:
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case ELF::R_MIPS_GPREL32:
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case ELF::R_MIPS_SHIFT5:
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case ELF::R_MIPS_SHIFT6:
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return false;
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default:
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llvm_unreachable("unknown Mips relocation type");
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}
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}
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return 0;
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}
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unsigned MipsELFWriterInfo::getAbsoluteLabelMachineRelTy() const {
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assert("getAbsoluteLabelMachineRelTy unknown for this relocation type");
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return 0;
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}
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long int MipsELFWriterInfo::computeRelocation(unsigned SymOffset,
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unsigned RelOffset,
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unsigned RelTy) const {
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if (RelTy == ELF::R_MIPS_PC16)
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return SymOffset - (RelOffset + 4);
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else
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assert("computeRelocation unknown for this relocation type");
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return 0;
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}
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@ -1,60 +0,0 @@
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//===-- MipsELFWriterInfo.h - ELF Writer Info for Mips ----------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements ELF writer information for the Mips backend.
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//
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//===----------------------------------------------------------------------===//
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#ifndef Mips_ELF_WRITER_INFO_H
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#define Mips_ELF_WRITER_INFO_H
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#include "llvm/Target/TargetELFWriterInfo.h"
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namespace llvm {
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class MipsELFWriterInfo : public TargetELFWriterInfo {
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public:
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MipsELFWriterInfo(bool, bool);
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virtual ~MipsELFWriterInfo();
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/// getRelocationType - Returns the target specific ELF Relocation type.
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/// 'MachineRelTy' contains the object code independent relocation type
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virtual unsigned getRelocationType(unsigned MachineRelTy) const;
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/// hasRelocationAddend - True if the target uses an addend in the
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/// ELF relocation entry.
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virtual bool hasRelocationAddend() const { return true; }
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// FIXME Should be case by case
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/// getDefaultAddendForRelTy - Gets the default addend value for a
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/// relocation entry based on the target ELF relocation type.
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virtual long int getDefaultAddendForRelTy(unsigned RelTy,
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long int Modifier = 0) const;
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/// getRelTySize - Returns the size of relocatable field in bits
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virtual unsigned getRelocationTySize(unsigned RelTy) const;
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/// isPCRelativeRel - True if the relocation type is pc relative
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virtual bool isPCRelativeRel(unsigned RelTy) const;
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/// getJumpTableRelocationTy - Returns the machine relocation type used
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/// to reference a jumptable.
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virtual unsigned getAbsoluteLabelMachineRelTy() const;
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/// computeRelocation - Some relocatable fields could be relocated
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/// directly, avoiding the relocation symbol emission, compute the
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/// final relocation value for this symbol.
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virtual long int computeRelocation(unsigned SymOffset, unsigned RelOffset,
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unsigned RelTy) const;
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};
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} // end llvm namespace
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#endif // Mips_ELF_WRITER_INFO_H
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@ -33,29 +33,7 @@ namespace llvm {
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reloc_mips_lo = 3,
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// reloc_mips_26 - lower 28 bits of the address, shifted right by 2.
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reloc_mips_26 = 4,
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// I am starting here with the rest of the relocations because
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// I have no idea if the above enumerations are assumed somewhere
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// else
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reloc_mips_16 = 6, // R_MIPS_16
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reloc_mips_32 = 7, // R_MIPS_32
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reloc_mips_rel32 = 8, // R_MIPS_REL32
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reloc_mips_gprel16 = 10, // R_MIPS_GPREL16
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reloc_mips_literal = 12, // R_MIPS_LITERAL
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reloc_mips_got16 = 13, // R_MIPS_GOT16
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reloc_mips_call16 = 15, // R_MIPS_CALL16
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reloc_mips_gprel32 = 17, // R_MIPS_GPREL32
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reloc_mips_shift5 = 18, // R_MIPS_SHIFT5
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reloc_mips_shift6 = 19, // R_MIPS_SHIFT6
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reloc_mips_64 = 20, // R_MIPS_64
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reloc_mips_tlsgd = 21, // R_MIPS_TLS_GD
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reloc_mips_gottprel = 22, // R_MIPS_TLS_GOTTPREL
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reloc_mips_tprel_hi = 23, // R_MIPS_TLS_TPREL_HI16
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reloc_mips_tprel_lo = 24, // R_MIPS_TLS_TPREL_LO16
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reloc_mips_branch_pcrel = 25, // This should become R_MIPS_PC16
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reloc_mips_pcrel = 26, // R_MIPS_PC16
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reloc_mips_j_jal = 27 // R_MIPS_26
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reloc_mips_26 = 4
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};
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}
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}
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