[mips][msa] Direct Object Emission of INSVE.{b,h,w,d}.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192587 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matheus Almeida 2013-10-14 12:38:17 +00:00
parent 29adbe8464
commit 01436ba306
2 changed files with 36 additions and 14 deletions

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@ -1263,23 +1263,23 @@ class MSA_INSERT_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
} }
class MSA_INSERT_PSEUDO_BASE<SDPatternOperator OpNode, ValueType Ty, class MSA_INSERT_PSEUDO_BASE<SDPatternOperator OpNode, ValueType Ty,
RegisterClass RCWD, RegisterClass RCFS> : RegisterOperand ROWD, RegisterOperand ROFS> :
MipsPseudo<(outs RCWD:$wd), (ins RCWD:$wd_in, uimm6:$n, RCFS:$fs), MipsPseudo<(outs ROWD:$wd), (ins ROWD:$wd_in, uimm6:$n, ROFS:$fs),
[(set RCWD:$wd, (OpNode (Ty RCWD:$wd_in), RCFS:$fs, [(set ROWD:$wd, (OpNode (Ty ROWD:$wd_in), ROFS:$fs,
immZExt6:$n))]> { immZExt6:$n))]> {
bit usesCustomInserter = 1; bit usesCustomInserter = 1;
string Constraints = "$wd = $wd_in"; string Constraints = "$wd = $wd_in";
} }
class MSA_INSVE_DESC_BASE<string instr_asm, SDPatternOperator OpNode, class MSA_INSVE_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
RegisterClass RCWD, RegisterClass RCWS = RCWD, RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
InstrItinClass itin = NoItinerary> { InstrItinClass itin = NoItinerary> {
dag OutOperandList = (outs RCWD:$wd); dag OutOperandList = (outs ROWD:$wd);
dag InOperandList = (ins RCWD:$wd_in, uimm6:$n, RCWS:$ws); dag InOperandList = (ins ROWD:$wd_in, uimm6:$n, ROWS:$ws);
string AsmString = !strconcat(instr_asm, "\t$wd[$n], $ws[0]"); string AsmString = !strconcat(instr_asm, "\t$wd[$n], $ws[0]");
list<dag> Pattern = [(set RCWD:$wd, (OpNode RCWD:$wd_in, list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in,
immZExt6:$n, immZExt6:$n,
RCWS:$ws))]; ROWS:$ws))];
InstrItinClass Itinerary = itin; InstrItinClass Itinerary = itin;
string Constraints = "$wd = $wd_in"; string Constraints = "$wd = $wd_in";
} }
@ -1983,14 +1983,18 @@ class INSERT_W_DESC : MSA_INSERT_DESC_BASE<"insert.w", vinsert_v4i32,
MSA128WOpnd, GPR32Opnd>; MSA128WOpnd, GPR32Opnd>;
class INSERT_FW_PSEUDO_DESC : MSA_INSERT_PSEUDO_BASE<vector_insert, v4f32, class INSERT_FW_PSEUDO_DESC : MSA_INSERT_PSEUDO_BASE<vector_insert, v4f32,
MSA128W, FGR32>; MSA128WOpnd, FGR32Opnd>;
class INSERT_FD_PSEUDO_DESC : MSA_INSERT_PSEUDO_BASE<vector_insert, v2f64, class INSERT_FD_PSEUDO_DESC : MSA_INSERT_PSEUDO_BASE<vector_insert, v2f64,
MSA128D, FGR64>; MSA128DOpnd, FGR64Opnd>;
class INSVE_B_DESC : MSA_INSVE_DESC_BASE<"insve.b", int_mips_insve_b, MSA128B>; class INSVE_B_DESC : MSA_INSVE_DESC_BASE<"insve.b", int_mips_insve_b,
class INSVE_H_DESC : MSA_INSVE_DESC_BASE<"insve.h", int_mips_insve_h, MSA128H>; MSA128BOpnd>;
class INSVE_W_DESC : MSA_INSVE_DESC_BASE<"insve.w", int_mips_insve_w, MSA128W>; class INSVE_H_DESC : MSA_INSVE_DESC_BASE<"insve.h", int_mips_insve_h,
class INSVE_D_DESC : MSA_INSVE_DESC_BASE<"insve.d", int_mips_insve_d, MSA128D>; MSA128HOpnd>;
class INSVE_W_DESC : MSA_INSVE_DESC_BASE<"insve.w", int_mips_insve_w,
MSA128WOpnd>;
class INSVE_D_DESC : MSA_INSVE_DESC_BASE<"insve.d", int_mips_insve_d,
MSA128DOpnd>;
class LD_DESC_BASE<string instr_asm, SDPatternOperator OpNode, class LD_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
ValueType TyNode, RegisterClass RCWD, Operand MemOpnd = mem, ValueType TyNode, RegisterClass RCWD, Operand MemOpnd = mem,

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@ -0,0 +1,18 @@
# RUN: llvm-mc %s -triple=mipsel-unknown-linux -show-encoding -mcpu=mips32r2 -mattr=+msa -arch=mips | FileCheck %s
#
# RUN: llvm-mc %s -triple=mipsel-unknown-linux -mcpu=mips32r2 -mattr=+msa -arch=mips -filetype=obj -o - | llvm-objdump -d -triple=mipsel-unknown-linux -mattr=+msa -arch=mips - | FileCheck %s -check-prefix=CHECKOBJDUMP
#
# CHECK: insve.b $w25[3], $w9[0] # encoding: [0x79,0x43,0x4e,0x59]
# CHECK: insve.h $w24[2], $w2[0] # encoding: [0x79,0x62,0x16,0x19]
# CHECK: insve.w $w0[2], $w13[0] # encoding: [0x79,0x72,0x68,0x19]
# CHECK: insve.d $w3[0], $w18[0] # encoding: [0x79,0x78,0x90,0xd9]
# CHECKOBJDUMP: insve.b $w25[3], $w9[0]
# CHECKOBJDUMP: insve.h $w24[2], $w2[0]
# CHECKOBJDUMP: insve.w $w0[2], $w13[0]
# CHECKOBJDUMP: insve.d $w3[0], $w18[0]
insve.b $w25[3], $w9[0]
insve.h $w24[2], $w2[0]
insve.w $w0[2], $w13[0]
insve.d $w3[0], $w18[0]