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MC/X86: Rename alternate spellings of {ADD64,CMP64} and mark as "code gen only" so they don't get selected by the asm matcher.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98972 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Daniel Dunbar 2010-03-19 18:07:48 +00:00
parent 7a68e0df0d
commit 0180daee02
2 changed files with 20 additions and 8 deletions
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24
lib/Target/X86/X86Instr64bit.td
View File

@ -511,6 +511,14 @@ def ADD64rr : RI<0x01, MRMDestReg, (outs GR64:$dst),
[(set GR64:$dst, (add GR64:$src1, GR64:$src2)),
(implicit EFLAGS)]>;
// These are alternate spellings for use by the disassembler, we mark them as
// code gen only to ensure they aren't matched by the assembler.
let isCodeGenOnly = 1 in {
def ADD64rr_alt : RI<0x03, MRMSrcReg, (outs GR64:$dst),
(ins GR64:$src1, GR64:$src2),
"add{l}\t{$src2, $dst|$dst, $src2}", []>;
}
// Register-Integer Addition
def ADD64ri8 : RIi8<0x83, MRM0r, (outs GR64:$dst),
(ins GR64:$src1, i64i8imm:$src2),
@ -531,12 +539,6 @@ def ADD64rm : RI<0x03, MRMSrcMem, (outs GR64:$dst),
[(set GR64:$dst, (add GR64:$src1, (load addr:$src2))),
(implicit EFLAGS)]>;
// Register-Register Addition - Equivalent to the normal rr form (ADD64rr), but
// differently encoded.
def ADD64mrmrr : RI<0x03, MRMSrcReg, (outs GR64:$dst),
(ins GR64:$src1, GR64:$src2),
"add{l}\t{$src2, $dst|$dst, $src2}", []>;
} // isTwoAddress
// Memory-Register Addition
@ -1249,8 +1251,14 @@ def CMP64i32 : RIi32<0x3D, RawFrm, (outs), (ins i32imm:$src),
def CMP64rr : RI<0x39, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
"cmp{q}\t{$src2, $src1|$src1, $src2}",
[(set EFLAGS, (X86cmp GR64:$src1, GR64:$src2))]>;
def CMP64mrmrr : RI<0x3B, MRMSrcReg, (outs), (ins GR64:$src1, GR64:$src2),
"cmp{q}\t{$src2, $src1|$src1, $src2}", []>;
// These are alternate spellings for use by the disassembler, we mark them as
// code gen only to ensure they aren't matched by the assembler.
let isCodeGenOnly = 1 in {
def CMP64mrmrr : RI<0x3B, MRMSrcReg, (outs), (ins GR64:$src1, GR64:$src2),
"cmp{q}\t{$src2, $src1|$src1, $src2}", []>;
}
def CMP64mr : RI<0x39, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
"cmp{q}\t{$src2, $src1|$src1, $src2}",
[(set EFLAGS, (X86cmp (loadi64 addr:$src1), GR64:$src2))]>;

4
test/MC/AsmParser/X86/x86_64-new-encoder.s
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@ -48,3 +48,7 @@ movq 0x00(%r13,%rax,8),%r13
// CHECK: testq %rax, %rbx
// CHECK: encoding: [0x48,0x85,0xd8]
testq %rax, %rbx
// CHECK: cmpq %rbx, %r14
// CHECK: encoding: [0x49,0x39,0xde]
cmpq %rbx, %r14