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[Hexagon] Changing some isCodeGenOnly to isAsmParserOnly since we want them to asm parse but not cause decode conflicts.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@228080 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Colin LeMahieu 2015-02-04 00:07:26 +00:00
parent a657cab9ec
commit 01ae000bf1
5 changed files with 39 additions and 40 deletions
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1
lib/Target/Hexagon/HexagonInstrFormats.td
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@ -192,7 +192,6 @@ class InstHexagon<dag outs, dag ins, string asmstr, list<dag> pattern,
""); "");
let PNewValue = !if(isPredicatedNew, "new", ""); let PNewValue = !if(isPredicatedNew, "new", "");
let NValueST = !if(isNVStore, "true", "false"); let NValueST = !if(isNVStore, "true", "false");
let isCodeGenOnly = 1;
// *** Must match MCTargetDesc/HexagonBaseInfo.h *** // *** Must match MCTargetDesc/HexagonBaseInfo.h ***
} }

44
lib/Target/Hexagon/HexagonInstrInfo.td
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@ -650,19 +650,19 @@ def A2_tfrsi : ALU32Inst<(outs IntRegs:$Rd), (ins s16Ext:$s16), "$Rd = #$s16",
let isCodeGenOnly = 0 in let isCodeGenOnly = 0 in
defm A2_tfr : tfr_base<"TFR">, ImmRegRel, PredNewRel; defm A2_tfr : tfr_base<"TFR">, ImmRegRel, PredNewRel;
let isCodeGenOnly = 1 in let isAsmParserOnly = 1 in
defm A2_tfrp : TFR64_base<"TFR64">, PredNewRel; defm A2_tfrp : TFR64_base<"TFR64">, PredNewRel;
// Assembler mapped // Assembler mapped
let isReMaterializable = 1, isMoveImm = 1, isAsCheapAsAMove = 1, let isReMaterializable = 1, isMoveImm = 1, isAsCheapAsAMove = 1,
isCodeGenOnly = 1 in isAsmParserOnly = 1 in
def A2_tfrpi : ALU64_rr<(outs DoubleRegs:$dst), (ins s8Imm64:$src1), def A2_tfrpi : ALU64_rr<(outs DoubleRegs:$dst), (ins s8Imm64:$src1),
"$dst = #$src1", "$dst = #$src1",
[(set (i64 DoubleRegs:$dst), s8Imm64Pred:$src1)]>; [(set (i64 DoubleRegs:$dst), s8Imm64Pred:$src1)]>;
// TODO: see if this instruction can be deleted.. // TODO: see if this instruction can be deleted..
let isExtendable = 1, opExtendable = 1, opExtentBits = 6, let isExtendable = 1, opExtendable = 1, opExtentBits = 6,
isCodeGenOnly = 1 in isAsmParserOnly = 1 in
def TFRI64_V4 : ALU64_rr<(outs DoubleRegs:$dst), (ins u6Ext:$src1), def TFRI64_V4 : ALU64_rr<(outs DoubleRegs:$dst), (ins u6Ext:$src1),
"$dst = #$src1">; "$dst = #$src1">;
@ -2689,7 +2689,7 @@ def M2_mpyui : MInst<(outs IntRegs:$dst),
// depending on the value of m9. See Arch Spec. // depending on the value of m9. See Arch Spec.
let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 9, let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 9,
CextOpcode = "mpyi", InputType = "imm", hasNewValue = 1, CextOpcode = "mpyi", InputType = "imm", hasNewValue = 1,
isCodeGenOnly = 1 in isAsmParserOnly = 1 in
def M2_mpysmi : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, s9Ext:$src2), def M2_mpysmi : MInst<(outs IntRegs:$dst), (ins IntRegs:$src1, s9Ext:$src2),
"$dst = mpyi($src1, #$src2)", "$dst = mpyi($src1, #$src2)",
[(set (i32 IntRegs:$dst), (mul (i32 IntRegs:$src1), [(set (i32 IntRegs:$dst), (mul (i32 IntRegs:$src1),
@ -4025,7 +4025,7 @@ def S2_asl_i_r_sat : T_S2op_2_ii <"asl", 0b010, 0b010, 1>;
let isCodeGenOnly = 0 in let isCodeGenOnly = 0 in
def S2_asr_i_r_rnd : T_S2op_2_ii <"asr", 0b010, 0b000, 0, 1>; def S2_asr_i_r_rnd : T_S2op_2_ii <"asr", 0b010, 0b000, 0, 1>;
let isCodeGenOnly = 1 in let isAsmParserOnly = 1 in
def S2_asr_i_r_rnd_goodsyntax def S2_asr_i_r_rnd_goodsyntax
: SInst <(outs IntRegs:$dst), (ins IntRegs:$src, u5Imm:$u5), : SInst <(outs IntRegs:$dst), (ins IntRegs:$src, u5Imm:$u5),
"$dst = asrrnd($src, #$u5)", "$dst = asrrnd($src, #$u5)",
@ -4684,51 +4684,51 @@ def HexagonCONST32_GP : SDNode<"HexagonISD::CONST32_GP", SDTHexagonCONST32>;
// HI/LO Instructions // HI/LO Instructions
let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0, let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0,
isCodeGenOnly = 1 in isAsmParserOnly = 1 in
def LO : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$global), def LO : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$global),
"$dst.l = #LO($global)", "$dst.l = #LO($global)",
[]>; []>;
let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0, let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0,
isCodeGenOnly = 1 in isAsmParserOnly = 1 in
def HI : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$global), def HI : ALU32_ri<(outs IntRegs:$dst), (ins globaladdress:$global),
"$dst.h = #HI($global)", "$dst.h = #HI($global)",
[]>; []>;
let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0, let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0,
isCodeGenOnly = 1 in isAsmParserOnly = 1 in
def LOi : ALU32_ri<(outs IntRegs:$dst), (ins i32imm:$imm_value), def LOi : ALU32_ri<(outs IntRegs:$dst), (ins i32imm:$imm_value),
"$dst.l = #LO($imm_value)", "$dst.l = #LO($imm_value)",
[]>; []>;
let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0, let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0,
isCodeGenOnly = 1 in isAsmParserOnly = 1 in
def HIi : ALU32_ri<(outs IntRegs:$dst), (ins i32imm:$imm_value), def HIi : ALU32_ri<(outs IntRegs:$dst), (ins i32imm:$imm_value),
"$dst.h = #HI($imm_value)", "$dst.h = #HI($imm_value)",
[]>; []>;
let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0, let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0,
isCodeGenOnly = 1 in isAsmParserOnly = 1 in
def LO_jt : ALU32_ri<(outs IntRegs:$dst), (ins jumptablebase:$jt), def LO_jt : ALU32_ri<(outs IntRegs:$dst), (ins jumptablebase:$jt),
"$dst.l = #LO($jt)", "$dst.l = #LO($jt)",
[]>; []>;
let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0, let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0,
isCodeGenOnly = 1 in isAsmParserOnly = 1 in
def HI_jt : ALU32_ri<(outs IntRegs:$dst), (ins jumptablebase:$jt), def HI_jt : ALU32_ri<(outs IntRegs:$dst), (ins jumptablebase:$jt),
"$dst.h = #HI($jt)", "$dst.h = #HI($jt)",
[]>; []>;
let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0, let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0,
isCodeGenOnly = 1 in isAsmParserOnly = 1 in
def LO_label : ALU32_ri<(outs IntRegs:$dst), (ins bblabel:$label), def LO_label : ALU32_ri<(outs IntRegs:$dst), (ins bblabel:$label),
"$dst.l = #LO($label)", "$dst.l = #LO($label)",
[]>; []>;
let isReMaterializable = 1, isMoveImm = 1 , hasSideEffects = 0, let isReMaterializable = 1, isMoveImm = 1 , hasSideEffects = 0,
isCodeGenOnly = 1 in isAsmParserOnly = 1 in
def HI_label : ALU32_ri<(outs IntRegs:$dst), (ins bblabel:$label), def HI_label : ALU32_ri<(outs IntRegs:$dst), (ins bblabel:$label),
"$dst.h = #HI($label)", "$dst.h = #HI($label)",
[]>; []>;
@ -4736,32 +4736,32 @@ def HI_label : ALU32_ri<(outs IntRegs:$dst), (ins bblabel:$label),
// This pattern is incorrect. When we add small data, we should change // This pattern is incorrect. When we add small data, we should change
// this pattern to use memw(#foo). // this pattern to use memw(#foo).
// This is for sdata. // This is for sdata.
let isMoveImm = 1, isCodeGenOnly = 1 in let isMoveImm = 1, isAsmParserOnly = 1 in
def CONST32 : LDInst<(outs IntRegs:$dst), (ins globaladdress:$global), def CONST32 : LDInst<(outs IntRegs:$dst), (ins globaladdress:$global),
"$dst = CONST32(#$global)", "$dst = CONST32(#$global)",
[(set (i32 IntRegs:$dst), [(set (i32 IntRegs:$dst),
(load (HexagonCONST32 tglobaltlsaddr:$global)))]>; (load (HexagonCONST32 tglobaltlsaddr:$global)))]>;
// This is for non-sdata. // This is for non-sdata.
let isReMaterializable = 1, isMoveImm = 1, isCodeGenOnly = 1 in let isReMaterializable = 1, isMoveImm = 1, isAsmParserOnly = 1 in
def CONST32_set : LDInst2<(outs IntRegs:$dst), (ins globaladdress:$global), def CONST32_set : LDInst2<(outs IntRegs:$dst), (ins globaladdress:$global),
"$dst = CONST32(#$global)", "$dst = CONST32(#$global)",
[(set (i32 IntRegs:$dst), [(set (i32 IntRegs:$dst),
(HexagonCONST32 tglobaladdr:$global))]>; (HexagonCONST32 tglobaladdr:$global))]>;
let isReMaterializable = 1, isMoveImm = 1, isCodeGenOnly = 1 in let isReMaterializable = 1, isMoveImm = 1, isAsmParserOnly = 1 in
def CONST32_set_jt : LDInst2<(outs IntRegs:$dst), (ins jumptablebase:$jt), def CONST32_set_jt : LDInst2<(outs IntRegs:$dst), (ins jumptablebase:$jt),
"$dst = CONST32(#$jt)", "$dst = CONST32(#$jt)",
[(set (i32 IntRegs:$dst), [(set (i32 IntRegs:$dst),
(HexagonCONST32 tjumptable:$jt))]>; (HexagonCONST32 tjumptable:$jt))]>;
let isReMaterializable = 1, isMoveImm = 1, isCodeGenOnly = 1 in let isReMaterializable = 1, isMoveImm = 1, isAsmParserOnly = 1 in
def CONST32GP_set : LDInst2<(outs IntRegs:$dst), (ins globaladdress:$global), def CONST32GP_set : LDInst2<(outs IntRegs:$dst), (ins globaladdress:$global),
"$dst = CONST32(#$global)", "$dst = CONST32(#$global)",
[(set (i32 IntRegs:$dst), [(set (i32 IntRegs:$dst),
(HexagonCONST32_GP tglobaladdr:$global))]>; (HexagonCONST32_GP tglobaladdr:$global))]>;
let isReMaterializable = 1, isMoveImm = 1, isCodeGenOnly = 1 in let isReMaterializable = 1, isMoveImm = 1, isAsmParserOnly = 1 in
def CONST32_Int_Real : LDInst2<(outs IntRegs:$dst), (ins i32imm:$global), def CONST32_Int_Real : LDInst2<(outs IntRegs:$dst), (ins i32imm:$global),
"$dst = CONST32(#$global)", "$dst = CONST32(#$global)",
[(set (i32 IntRegs:$dst), imm:$global) ]>; [(set (i32 IntRegs:$dst), imm:$global) ]>;
@ -4770,12 +4770,12 @@ def CONST32_Int_Real : LDInst2<(outs IntRegs:$dst), (ins i32imm:$global),
def : Pat<(HexagonCONST32_GP tblockaddress:$addr), def : Pat<(HexagonCONST32_GP tblockaddress:$addr),
(CONST32_Int_Real tblockaddress:$addr)>; (CONST32_Int_Real tblockaddress:$addr)>;
let isReMaterializable = 1, isMoveImm = 1, isCodeGenOnly = 1 in let isReMaterializable = 1, isMoveImm = 1, isAsmParserOnly = 1 in
def CONST32_Label : LDInst2<(outs IntRegs:$dst), (ins bblabel:$label), def CONST32_Label : LDInst2<(outs IntRegs:$dst), (ins bblabel:$label),
"$dst = CONST32($label)", "$dst = CONST32($label)",
[(set (i32 IntRegs:$dst), (HexagonCONST32 bbl:$label))]>; [(set (i32 IntRegs:$dst), (HexagonCONST32 bbl:$label))]>;
let isReMaterializable = 1, isMoveImm = 1, isCodeGenOnly = 1 in let isReMaterializable = 1, isMoveImm = 1, isAsmParserOnly = 1 in
def CONST64_Int_Real : LDInst2<(outs DoubleRegs:$dst), (ins i64imm:$global), def CONST64_Int_Real : LDInst2<(outs DoubleRegs:$dst), (ins i64imm:$global),
"$dst = CONST64(#$global)", "$dst = CONST64(#$global)",
[(set (i64 DoubleRegs:$dst), imm:$global) ]>; [(set (i64 DoubleRegs:$dst), imm:$global) ]>;
@ -4814,7 +4814,7 @@ let Defs = [R29, R30, R31], Uses = [R29] in {
[(callseq_end timm:$amt1, timm:$amt2)]>; [(callseq_end timm:$amt1, timm:$amt2)]>;
} }
// Call subroutine. // Call subroutine.
let isCall = 1, hasSideEffects = 0, isCodeGenOnly = 1, let isCall = 1, hasSideEffects = 0, isAsmParserOnly = 1,
Defs = [D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, Defs = [D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10,
R22, R23, R28, R31, P0, P1, P2, P3, LC0, LC1, SA0, SA1] in { R22, R23, R28, R31, P0, P1, P2, P3, LC0, LC1, SA0, SA1] in {
def CALL : JInst<(outs), (ins calltarget:$dst), def CALL : JInst<(outs), (ins calltarget:$dst),
@ -5404,7 +5404,7 @@ def SDTHexagonADJDYNALLOC : SDTypeProfile<1, 2,
def Hexagon_ADJDYNALLOC : SDNode<"HexagonISD::ADJDYNALLOC", def Hexagon_ADJDYNALLOC : SDNode<"HexagonISD::ADJDYNALLOC",
SDTHexagonADJDYNALLOC>; SDTHexagonADJDYNALLOC>;
// Needed to tag these instructions for stack layout. // Needed to tag these instructions for stack layout.
let usesCustomInserter = 1, isCodeGenOnly = 1 in let usesCustomInserter = 1, isAsmParserOnly = 1 in
def ADJDYNALLOC : ALU32_ri<(outs IntRegs:$dst), (ins IntRegs:$src1, def ADJDYNALLOC : ALU32_ri<(outs IntRegs:$dst), (ins IntRegs:$src1,
s16Imm:$src2), s16Imm:$src2),
"$dst = add($src1, #$src2)", "$dst = add($src1, #$src2)",

8
lib/Target/Hexagon/HexagonInstrInfoV3.td
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@ -106,7 +106,7 @@ def A2_addspl : T_ALU64_addsp_hl<":raw:lo", 0b110>;
def A2_addsph : T_ALU64_addsp_hl<":raw:hi", 0b111>; def A2_addsph : T_ALU64_addsp_hl<":raw:hi", 0b111>;
} }
let hasSideEffects = 0, isCodeGenOnly = 1 in let hasSideEffects = 0, isAsmParserOnly = 1 in
def A2_addsp : ALU64_rr<(outs DoubleRegs:$Rd), def A2_addsp : ALU64_rr<(outs DoubleRegs:$Rd),
(ins IntRegs:$Rs, DoubleRegs:$Rt), "$Rd = add($Rs, $Rt)", (ins IntRegs:$Rs, DoubleRegs:$Rt), "$Rd = add($Rs, $Rt)",
[(set (i64 DoubleRegs:$Rd), (i64 (add (i64 (sext (i32 IntRegs:$Rs))), [(set (i64 DoubleRegs:$Rd), (i64 (add (i64 (sext (i32 IntRegs:$Rs))),
@ -225,7 +225,7 @@ def M2_vrcmpys_s1_l: T_vrcmpRaw<"lo", 0b111>;
} }
// Assembler mapped to M2_vrcmpys_s1_h or M2_vrcmpys_s1_l // Assembler mapped to M2_vrcmpys_s1_h or M2_vrcmpys_s1_l
let hasSideEffects = 0, isCodeGenOnly = 1 in let hasSideEffects = 0, isAsmParserOnly = 1 in
def M2_vrcmpys_s1 def M2_vrcmpys_s1
: MInst<(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rss, IntRegs:$Rt), : MInst<(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rss, IntRegs:$Rt),
"$Rdd=vrcmpys($Rss,$Rt):<<1:sat">; "$Rdd=vrcmpys($Rss,$Rt):<<1:sat">;
@ -258,7 +258,7 @@ def M2_vrcmpys_acc_s1_l: T_vrcmpys_acc<"lo", 0b111>;
// Assembler mapped to M2_vrcmpys_acc_s1_h or M2_vrcmpys_acc_s1_l // Assembler mapped to M2_vrcmpys_acc_s1_h or M2_vrcmpys_acc_s1_l
let isCodeGenOnly = 1 in let isAsmParserOnly = 1 in
def M2_vrcmpys_acc_s1 def M2_vrcmpys_acc_s1
: MInst <(outs DoubleRegs:$dst), : MInst <(outs DoubleRegs:$dst),
(ins DoubleRegs:$dst2, DoubleRegs:$src1, IntRegs:$src2), (ins DoubleRegs:$dst2, DoubleRegs:$src1, IntRegs:$src2),
@ -271,7 +271,7 @@ def M2_vrcmpys_s1rp_l : T_MType_vrcmpy <"vrcmpys", 0b101, 0b111, 0>;
} }
// Assembler mapped to M2_vrcmpys_s1rp_h or M2_vrcmpys_s1rp_l // Assembler mapped to M2_vrcmpys_s1rp_h or M2_vrcmpys_s1rp_l
let isCodeGenOnly = 1 in let isAsmParserOnly = 1 in
def M2_vrcmpys_s1rp def M2_vrcmpys_s1rp
: MInst <(outs IntRegs:$Rd), (ins DoubleRegs:$Rss, IntRegs:$Rt), : MInst <(outs IntRegs:$Rd), (ins DoubleRegs:$Rss, IntRegs:$Rt),
"$Rd=vrcmpys($Rss,$Rt):<<1:rnd:sat">; "$Rd=vrcmpys($Rss,$Rt):<<1:rnd:sat">;

14
lib/Target/Hexagon/HexagonInstrInfoV4.td
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@ -3205,7 +3205,7 @@ defm L4_return: LD_MISC_L4_RETURN <"dealloc_return">, PredNewRel;
// Restore registers and dealloc return function call. // Restore registers and dealloc return function call.
let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1, let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1,
Defs = [R29, R30, R31, PC], isCodeGenOnly = 1 in { Defs = [R29, R30, R31, PC], isAsmParserOnly = 1 in {
let validSubTargets = HasV4SubT in let validSubTargets = HasV4SubT in
def RESTORE_DEALLOC_RET_JMP_V4 : JInst<(outs), def RESTORE_DEALLOC_RET_JMP_V4 : JInst<(outs),
(ins calltarget:$dst), (ins calltarget:$dst),
@ -3215,7 +3215,7 @@ let validSubTargets = HasV4SubT in
} }
// Restore registers and dealloc frame before a tail call. // Restore registers and dealloc frame before a tail call.
let isCall = 1, isBarrier = 1, isCodeGenOnly = 1, let isCall = 1, isBarrier = 1, isAsmParserOnly = 1,
Defs = [R29, R30, R31, PC] in { Defs = [R29, R30, R31, PC] in {
let validSubTargets = HasV4SubT in let validSubTargets = HasV4SubT in
def RESTORE_DEALLOC_BEFORE_TAILCALL_V4 : JInst<(outs), def RESTORE_DEALLOC_BEFORE_TAILCALL_V4 : JInst<(outs),
@ -3226,7 +3226,7 @@ let validSubTargets = HasV4SubT in
} }
// Save registers function call. // Save registers function call.
let isCall = 1, isBarrier = 1, isCodeGenOnly = 1, let isCall = 1, isBarrier = 1, isAsmParserOnly = 1,
Uses = [R29, R31] in { Uses = [R29, R31] in {
def SAVE_REGISTERS_CALL_V4 : JInst<(outs), def SAVE_REGISTERS_CALL_V4 : JInst<(outs),
(ins calltarget:$dst), (ins calltarget:$dst),
@ -3468,7 +3468,7 @@ defm storerf : ST_Abs <"memh", "STrif", IntRegs, u16_1Imm, 0b01, 1>;
// if ([!]Pv[.new]) mem[bhwd](##global)=Rt // if ([!]Pv[.new]) mem[bhwd](##global)=Rt
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
let validSubTargets = HasV4SubT, isCodeGenOnly = 1 in let validSubTargets = HasV4SubT, isAsmParserOnly = 1 in
class T_StoreGP <string mnemonic, string BaseOp, RegisterClass RC, class T_StoreGP <string mnemonic, string BaseOp, RegisterClass RC,
Operand ImmOp, bits<2> MajOp, bit isHalf = 0> Operand ImmOp, bits<2> MajOp, bit isHalf = 0>
: T_StoreAbsGP <mnemonic, RC, ImmOp, MajOp, globaladdress, 0, isHalf> { : T_StoreAbsGP <mnemonic, RC, ImmOp, MajOp, globaladdress, 0, isHalf> {
@ -3478,7 +3478,7 @@ class T_StoreGP <string mnemonic, string BaseOp, RegisterClass RC,
let BaseOpcode = BaseOp#_abs; let BaseOpcode = BaseOp#_abs;
} }
let validSubTargets = HasV4SubT, isCodeGenOnly = 1 in let validSubTargets = HasV4SubT, isAsmParserOnly = 1 in
multiclass ST_GP <string mnemonic, string BaseOp, Operand ImmOp, multiclass ST_GP <string mnemonic, string BaseOp, Operand ImmOp,
bits<2> MajOp, bit isHalf = 0> { bits<2> MajOp, bit isHalf = 0> {
// Set BaseOpcode same as absolute addressing instructions so that // Set BaseOpcode same as absolute addressing instructions so that
@ -3698,7 +3698,7 @@ defm loadrd : LD_Abs<"memd", "LDrid", DoubleRegs, u16_3Imm, 0b110>;
// if ([!]Pv[.new]) Rx=mem[bhwd](##global) // if ([!]Pv[.new]) Rx=mem[bhwd](##global)
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
let isCodeGenOnly = 1 in let isAsmParserOnly = 1 in
class T_LoadGP <string mnemonic, string BaseOp, RegisterClass RC, Operand ImmOp, class T_LoadGP <string mnemonic, string BaseOp, RegisterClass RC, Operand ImmOp,
bits<3> MajOp> bits<3> MajOp>
: T_LoadAbsGP <mnemonic, RC, ImmOp, MajOp, globaladdress, 0>, PredNewRel { : T_LoadAbsGP <mnemonic, RC, ImmOp, MajOp, globaladdress, 0>, PredNewRel {
@ -4192,7 +4192,7 @@ def A4_boundscheck_hi: ALU64Inst <
let Inst{12-8} = Rtt; let Inst{12-8} = Rtt;
} }
let hasSideEffects = 0, isCodeGenOnly = 1 in let hasSideEffects = 0, isAsmParserOnly = 1 in
def A4_boundscheck : MInst < def A4_boundscheck : MInst <
(outs PredRegs:$Pd), (ins IntRegs:$Rs, DoubleRegs:$Rtt), (outs PredRegs:$Pd), (ins IntRegs:$Rs, DoubleRegs:$Rtt),
"$Pd=boundscheck($Rs,$Rtt)">; "$Pd=boundscheck($Rs,$Rtt)">;

12
lib/Target/Hexagon/HexagonInstrInfoV5.td
View File

@ -53,7 +53,7 @@ def S2_asr_i_p_rnd : S_2OpInstImm<"asr", 0b110, 0b111, u6Imm,
let Inst{13-8} = src2; let Inst{13-8} = src2;
} }
let isCodeGenOnly = 1 in let isAsmParserOnly = 1 in
def S2_asr_i_p_rnd_goodsyntax def S2_asr_i_p_rnd_goodsyntax
: MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6Imm:$src2), : MInst<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1, u6Imm:$src2),
"$dst = asrrnd($src1, #$src2)">; "$dst = asrrnd($src1, #$src2)">;
@ -75,20 +75,20 @@ def SDTHexagonFCONST32 : SDTypeProfile<1, 1, [
SDTCisPtrTy<1>]>; SDTCisPtrTy<1>]>;
def HexagonFCONST32 : SDNode<"HexagonISD::FCONST32", SDTHexagonFCONST32>; def HexagonFCONST32 : SDNode<"HexagonISD::FCONST32", SDTHexagonFCONST32>;
let isReMaterializable = 1, isMoveImm = 1, isCodeGenOnly = 1 in let isReMaterializable = 1, isMoveImm = 1, isAsmParserOnly = 1 in
def FCONST32_nsdata : LDInst<(outs IntRegs:$dst), (ins globaladdress:$global), def FCONST32_nsdata : LDInst<(outs IntRegs:$dst), (ins globaladdress:$global),
"$dst = CONST32(#$global)", "$dst = CONST32(#$global)",
[(set (f32 IntRegs:$dst), [(set (f32 IntRegs:$dst),
(HexagonFCONST32 tglobaladdr:$global))]>, (HexagonFCONST32 tglobaladdr:$global))]>,
Requires<[HasV5T]>; Requires<[HasV5T]>;
let isReMaterializable = 1, isMoveImm = 1, isCodeGenOnly = 1 in let isReMaterializable = 1, isMoveImm = 1, isAsmParserOnly = 1 in
def CONST64_Float_Real : LDInst<(outs DoubleRegs:$dst), (ins f64imm:$src1), def CONST64_Float_Real : LDInst<(outs DoubleRegs:$dst), (ins f64imm:$src1),
"$dst = CONST64(#$src1)", "$dst = CONST64(#$src1)",
[(set DoubleRegs:$dst, fpimm:$src1)]>, [(set DoubleRegs:$dst, fpimm:$src1)]>,
Requires<[HasV5T]>; Requires<[HasV5T]>;
let isReMaterializable = 1, isMoveImm = 1, isCodeGenOnly = 1 in let isReMaterializable = 1, isMoveImm = 1, isAsmParserOnly = 1 in
def CONST32_Float_Real : LDInst<(outs IntRegs:$dst), (ins f32imm:$src1), def CONST32_Float_Real : LDInst<(outs IntRegs:$dst), (ins f32imm:$src1),
"$dst = CONST32(#$src1)", "$dst = CONST32(#$src1)",
[(set IntRegs:$dst, fpimm:$src1)]>, [(set IntRegs:$dst, fpimm:$src1)]>,
@ -785,7 +785,7 @@ def S5_asrhub_rnd_sat : T_ASRHUB <0>;
def S5_asrhub_sat : T_ASRHUB <1>; def S5_asrhub_sat : T_ASRHUB <1>;
} }
let isCodeGenOnly = 1 in let isAsmParserOnly = 1 in
def S5_asrhub_rnd_sat_goodsyntax def S5_asrhub_rnd_sat_goodsyntax
: SInst <(outs IntRegs:$Rd), (ins DoubleRegs:$Rss, u4Imm:$u4), : SInst <(outs IntRegs:$Rd), (ins DoubleRegs:$Rss, u4Imm:$u4),
"$Rd = vasrhub($Rss, #$u4):rnd:sat">, Requires<[HasV5T]>; "$Rd = vasrhub($Rss, #$u4):rnd:sat">, Requires<[HasV5T]>;
@ -810,7 +810,7 @@ def S5_vasrhrnd : SInst <(outs DoubleRegs:$Rdd),
let Inst{4-0} = Rdd; let Inst{4-0} = Rdd;
} }
let isCodeGenOnly = 1 in let isAsmParserOnly = 1 in
def S5_vasrhrnd_goodsyntax def S5_vasrhrnd_goodsyntax
: SInst <(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rss, u4Imm:$u4), : SInst <(outs DoubleRegs:$Rdd), (ins DoubleRegs:$Rss, u4Imm:$u4),
"$Rdd = vasrh($Rss,#$u4):rnd">, Requires<[HasV5T]>; "$Rdd = vasrh($Rss,#$u4):rnd">, Requires<[HasV5T]>;