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ARM: Fix TPsoft for Thumb mode

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Reviewed at http://reviews.llvm.org/D4230



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211601 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Christian Pirker 2014-06-24 15:45:59 +00:00
parent 9a0f931b9d
commit 01c8340c3d
3 changed files with 67 additions and 5 deletions
lib/Target/ARM
ARMExpandPseudoInsts.cppARMInstrInfo.td
test/CodeGen/Thumb2
tpsoft.ll

14
lib/Target/ARM/ARMExpandPseudoInsts.cpp

@ -927,10 +927,16 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
}
case ARM::tTPsoft:
case ARM::TPsoft: {
MachineInstrBuilder MIB =
BuildMI(MBB, MBBI, MI.getDebugLoc(),
TII->get(Opcode == ARM::tTPsoft ? ARM::tBL : ARM::BL))
.addExternalSymbol("__aeabi_read_tp", 0);
MachineInstrBuilder MIB;
if (Opcode == ARM::tTPsoft)
MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
TII->get( ARM::tBL))
.addImm((unsigned)ARMCC::AL).addReg(0)
.addExternalSymbol("__aeabi_read_tp", 0);
else
MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
TII->get( ARM::BL))
.addExternalSymbol("__aeabi_read_tp", 0);
MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
TransferImpOps(MI, MIB, MIB);

4
lib/Target/ARM/ARMInstrInfo.td

@ -5113,9 +5113,11 @@ let usesCustomInserter = 1, Uses = [R4], Defs = [R4, SP] in
// __aeabi_read_tp preserves the registers r1-r3.
// This is a pseudo inst so that we can get the encoding right,
// complete with fixup for the aeabi_read_tp function.
// TPsoft is valid for ARM mode only, in case of Thumb mode a tTPsoft pattern
// is defined in "ARMInstrThumb.td".
let isCall = 1,
Defs = [R0, R12, LR, CPSR], Uses = [SP] in {
def TPsoft : PseudoInst<(outs), (ins), IIC_Br,
def TPsoft : ARMPseudoInst<(outs), (ins), 4, IIC_Br,
[(set R0, ARMthread_pointer)]>, Sched<[WriteBr]>;
}

54
test/CodeGen/Thumb2/tpsoft.ll Normal file

@ -0,0 +1,54 @@
; RUN: llc %s -mtriple=thumbv7-linux-gnueabi -o - | \
; RUN: FileCheck -check-prefix=ELFASM %s
; RUN: llc %s -mtriple=thumbebv7-linux-gnueabi -o - | \
; RUN: FileCheck -check-prefix=ELFASM %s
; RUN: llc %s -mtriple=thumbv7-linux-gnueabi -filetype=obj -o - | \
; RUN: llvm-readobj -s -sd | FileCheck -check-prefix=ELFOBJ -check-prefix=ELFOBJ-LE %s
; RUN: llc %s -mtriple=thumbebv7-linux-gnueabi -filetype=obj -o - | \
; RUN: llvm-readobj -s -sd | FileCheck -check-prefix=ELFOBJ -check-prefix=ELFOBJ-BE %s
;; Make sure that bl __aeabi_read_tp is materialized and fixed up correctly
;; in the obj case.
@i = external thread_local global i32
@a = external global i8
@b = external global [10 x i8]
define arm_aapcs_vfpcc i32 @main() nounwind {
entry:
%0 = load i32* @i, align 4
switch i32 %0, label %bb2 [
i32 12, label %bb
i32 13, label %bb1
]
bb: ; preds = %entry
%1 = tail call arm_aapcs_vfpcc i32 @foo(i8* @a) nounwind
ret i32 %1
; ELFASM: bl __aeabi_read_tp
; ELFOBJ: Sections [
; ELFOBJ: Section {
; ELFOBJ: Name: .text
; ELFOBJ-LE: SectionData (
;;; BL __aeabi_read_tp is ---------+
;;; V
; ELFOBJ-LE-NEXT: 0000: 2DE90048 0E487844 0168FFF7 FEFF4058
; ELFOBJ-BE: SectionData (
;;; BL __aeabi_read_tp is ---------+
;;; V
; ELFOBJ-BE-NEXT: 0000: E92D4800 480E4478 6801F7FF FFFE5840
bb1: ; preds = %entry
%2 = tail call arm_aapcs_vfpcc i32 @bar(i32* bitcast ([10 x i8]* @b to i32*)) nounwind
ret i32 %2
bb2: ; preds = %entry
ret i32 -1
}
declare arm_aapcs_vfpcc i32 @foo(i8*)
declare arm_aapcs_vfpcc i32 @bar(i32*)