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Make sure to mark unsupported SCALAR_TO_VECTOR operations as expand.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27385 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2006-04-03 23:55:43 +00:00
parent 97ac5fadb7
commit 01cae0799d
1 changed files with 5 additions and 1 deletions
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6
lib/Target/PowerPC/PPCISelLowering.cpp
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@ -182,7 +182,7 @@ PPCTargetLowering::PPCTargetLowering(TargetMachine &TM)
setOperationAction(ISD::XOR , (MVT::ValueType)VT, Legal);
// We can custom expand all VECTOR_SHUFFLEs to VPERM.
setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Custom);
setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Promote);
setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand);
setOperationAction(ISD::SDIV, (MVT::ValueType)VT, Expand);
@ -192,8 +192,12 @@ PPCTargetLowering::PPCTargetLowering(TargetMachine &TM)
setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Expand);
setOperationAction(ISD::SCALAR_TO_VECTOR, (MVT::ValueType)VT, Expand);
}
setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass);
addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass);
addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass);