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Mark x86 _alt instructions as AsmParserOnly so they will be omitted from disassembler without string matches.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@198545 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper 2014-01-05 04:55:55 +00:00
parent 2b5dc93948
commit 01cb7fa977
3 changed files with 6 additions and 7 deletions
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6
lib/Target/X86/X86InstrAVX512.td
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@ -701,7 +701,7 @@ multiclass avx512_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
(outs VK1:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm, (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
[(set VK1:$dst, (OpNode (VT RC:$src1), [(set VK1:$dst, (OpNode (VT RC:$src1),
(ld_frag addr:$src2), imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V; (ld_frag addr:$src2), imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
let neverHasSideEffects = 1 in { let isAsmParserOnly = 1, hasSideEffects = 0 in {
def rri_alt : AVX512Ii8<0xC2, MRMSrcReg, def rri_alt : AVX512Ii8<0xC2, MRMSrcReg,
(outs VK1:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc), (outs VK1:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
asm_alt, [], IIC_SSE_ALU_F32S_RR>, EVEX_4V; asm_alt, [], IIC_SSE_ALU_F32S_RR>, EVEX_4V;
@ -770,7 +770,7 @@ multiclass avx512_icmp_cc<bits<8> opc, RegisterClass KRC,
[(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2), [(set KRC:$dst, (OpNode (vt RC:$src1), (memop_frag addr:$src2),
imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V; imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
// Accept explicit immediate argument form instead of comparison code. // Accept explicit immediate argument form instead of comparison code.
let neverHasSideEffects = 1 in { let isAsmParserOnly = 1, hasSideEffects = 0 in {
def rri_alt : AVX512AIi8<opc, MRMSrcReg, def rri_alt : AVX512AIi8<opc, MRMSrcReg,
(outs KRC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc), (outs KRC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
asm_alt, [], IIC_SSE_ALU_F32P_RR>, EVEX_4V; asm_alt, [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
@ -824,7 +824,7 @@ multiclass avx512_cmp_packed<RegisterClass KRC, RegisterClass RC,
(X86cmpm (vt RC:$src1), (memop addr:$src2), imm:$cc))], d>; (X86cmpm (vt RC:$src1), (memop addr:$src2), imm:$cc))], d>;
// Accept explicit immediate argument form instead of comparison code. // Accept explicit immediate argument form instead of comparison code.
let neverHasSideEffects = 1 in { let isAsmParserOnly = 1, hasSideEffects = 0 in {
def rri_alt : AVX512PIi8<0xC2, MRMSrcReg, def rri_alt : AVX512PIi8<0xC2, MRMSrcReg,
(outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc), (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
!strconcat("vcmp", suffix, !strconcat("vcmp", suffix,

4
lib/Target/X86/X86InstrSSE.td
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@ -2299,7 +2299,7 @@ multiclass sse12_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
Sched<[itins.Sched.Folded, ReadAfterLd]>; Sched<[itins.Sched.Folded, ReadAfterLd]>;
// Accept explicit immediate argument form instead of comparison code. // Accept explicit immediate argument form instead of comparison code.
let neverHasSideEffects = 1 in { let isAsmParserOnly = 1, hasSideEffects = 0 in {
def rr_alt : SIi8<0xC2, MRMSrcReg, (outs RC:$dst), def rr_alt : SIi8<0xC2, MRMSrcReg, (outs RC:$dst),
(ins RC:$src1, RC:$src2, i8imm:$cc), asm_alt, [], (ins RC:$src1, RC:$src2, i8imm:$cc), asm_alt, [],
IIC_SSE_ALU_F32S_RR>, Sched<[itins.Sched]>; IIC_SSE_ALU_F32S_RR>, Sched<[itins.Sched]>;
@ -2454,7 +2454,7 @@ multiclass sse12_cmp_packed<RegisterClass RC, X86MemOperand x86memop,
Sched<[WriteFAddLd, ReadAfterLd]>; Sched<[WriteFAddLd, ReadAfterLd]>;
// Accept explicit immediate argument form instead of comparison code. // Accept explicit immediate argument form instead of comparison code.
let neverHasSideEffects = 1 in { let isAsmParserOnly = 1, hasSideEffects = 0 in {
def rri_alt : PIi8<0xC2, MRMSrcReg, def rri_alt : PIi8<0xC2, MRMSrcReg,
(outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc), (outs RC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
asm_alt, [], itins.rr, d>, Sched<[WriteFAdd]>; asm_alt, [], itins.rr, d>, Sched<[WriteFAdd]>;

3
utils/TableGen/X86RecognizableInstr.cpp
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@ -508,8 +508,7 @@ RecognizableInstr::filter_ret RecognizableInstr::filter() const {
return FILTER_WEAK; return FILTER_WEAK;
// Filter out alternate forms of AVX instructions // Filter out alternate forms of AVX instructions
if (Name.find("_alt") != Name.npos || if ((Name.find("r64r") != Name.npos && Name.find("r64r64") == Name.npos && Name.find("r64r8") == Name.npos) ||
(Name.find("r64r") != Name.npos && Name.find("r64r64") == Name.npos && Name.find("r64r8") == Name.npos) ||
Name.find("_64mr") != Name.npos || Name.find("_64mr") != Name.npos ||
Name.find("rr64") != Name.npos) Name.find("rr64") != Name.npos)
return FILTER_WEAK; return FILTER_WEAK;