6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-02-11 11:34:02 +00:00
Code Issues Projects Releases Wiki Activity

Expand invalid return values for umulo and smulo. Handle these similarly

Browse Source 
to add/sub by doing the normal operation and then checking for overflow
afterwards. This generally relies on the DAG handling the later invalid
operations as well.

Fixes the 64-bit part of rdar://8622122 and rdar://8774702.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123908 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eric Christopher 2011-01-20 08:54:28 +00:00
parent 907276dc44
commit 02050986d9
3 changed files with 56 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

27
lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
View File

@ -1057,6 +1057,8 @@ void DAGTypeLegalizer::ExpandIntegerResult(SDNode *N, unsigned ResNo) {
case ISD::SSUBO: ExpandIntRes_SADDSUBO(N, Lo, Hi); break;
case ISD::UADDO:
case ISD::USUBO: ExpandIntRes_UADDSUBO(N, Lo, Hi); break;
case ISD::UMULO:
case ISD::SMULO: ExpandIntRes_UMULSMULO(N, Lo, Hi); break;
}
// If Lo/Hi is null, the sub-method took care of registering results etc.
@ -2132,6 +2134,31 @@ void DAGTypeLegalizer::ExpandIntRes_UADDSUBO(SDNode *N,
ReplaceValueWith(SDValue(N, 1), Ofl);
}
void DAGTypeLegalizer::ExpandIntRes_UMULSMULO(SDNode *N,
SDValue &Lo, SDValue &Hi) {
SDValue LHS = N->getOperand(0);
SDValue RHS = N->getOperand(1);
DebugLoc dl = N->getDebugLoc();
EVT VT = N->getValueType(0);
EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits() / 2);
// Expand the result by simply replacing it with the equivalent
// non-overflow-checking operation.
SDValue Ret = DAG.getNode(ISD::MUL, dl, LHS.getValueType(), LHS, RHS);
SplitInteger(Ret, Lo, Hi);
// Now calculate overflow.
SDValue Ofl;
if (N->getOpcode() == ISD::UMULO)
Ofl = DAG.getSetCC(dl, N->getValueType(1), Hi,
DAG.getConstant(0, VT), ISD::SETNE);
else {
SDValue Tmp = DAG.getConstant(VT.getSizeInBits() - 1, HalfVT);
Tmp = DAG.getNode(ISD::SRA, dl, HalfVT, Lo, Tmp);
Ofl = DAG.getSetCC(dl, N->getValueType(1), Hi, Tmp, ISD::SETNE);
}
ReplaceValueWith(SDValue(N, 1), Ofl);
}
void DAGTypeLegalizer::ExpandIntRes_UDIV(SDNode *N,
SDValue &Lo, SDValue &Hi) {
EVT VT = N->getValueType(0);

1
lib/CodeGen/SelectionDAG/LegalizeTypes.h
View File

@ -348,6 +348,7 @@ private:
void ExpandIntRes_SADDSUBO (SDNode *N, SDValue &Lo, SDValue &Hi);
void ExpandIntRes_UADDSUBO (SDNode *N, SDValue &Lo, SDValue &Hi);
void ExpandIntRes_UMULSMULO (SDNode *N, SDValue &Lo, SDValue &Hi);
void ExpandShiftByConstant(SDNode *N, unsigned Amt,
SDValue &Lo, SDValue &Hi);

28
test/CodeGen/X86/umulo-64.ll Normal file
View File

@ -0,0 +1,28 @@
; RUN: llc < %s -mtriple=i386-apple-darwin
%0 = type { i64, i1 }
define i32 @f0(i64 %a, i64 %b) nounwind ssp {
%1 = alloca i64, align 4
%2 = alloca i64, align 4
store i64 %a, i64* %1, align 8
store i64 %b, i64* %2, align 8
%3 = load i64* %1, align 8
%4 = load i64* %2, align 8
%5 = call %0 @llvm.smul.with.overflow.i64(i64 %3, i64 %4)
%6 = extractvalue %0 %5, 0
%7 = extractvalue %0 %5, 1
br i1 %7, label %8, label %9
; <label>:8 ; preds = %0
call void @llvm.trap()
unreachable
; <label>:9 ; preds = %0
%10 = trunc i64 %6 to i32
ret i32 %10
}
declare %0 @llvm.smul.with.overflow.i64(i64, i64) nounwind readnone
declare void @llvm.trap() nounwind