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--- Reverse-merging r107947 into '.':
U utils/TableGen/FastISelEmitter.cpp --- Reverse-merging r107943 into '.': U test/CodeGen/X86/fast-isel.ll U test/CodeGen/X86/fast-isel-loads.ll U include/llvm/Target/TargetLowering.h U include/llvm/Support/PassNameParser.h U include/llvm/CodeGen/FunctionLoweringInfo.h U include/llvm/CodeGen/CallingConvLower.h U include/llvm/CodeGen/FastISel.h U include/llvm/CodeGen/SelectionDAGISel.h U lib/CodeGen/LLVMTargetMachine.cpp U lib/CodeGen/CallingConvLower.cpp U lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp U lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp U lib/CodeGen/SelectionDAG/FastISel.cpp U lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp U lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp U lib/CodeGen/SelectionDAG/InstrEmitter.cpp U lib/CodeGen/SelectionDAG/TargetLowering.cpp U lib/Target/XCore/XCoreISelLowering.cpp U lib/Target/XCore/XCoreISelLowering.h U lib/Target/X86/X86ISelLowering.cpp U lib/Target/X86/X86FastISel.cpp U lib/Target/X86/X86ISelLowering.h git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107987 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -80,12 +80,13 @@ CCState::AnalyzeFormalArguments(const SmallVectorImpl<ISD::InputArg> &Ins,
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/// CheckReturn - Analyze the return values of a function, returning true if
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/// the return can be performed without sret-demotion, and false otherwise.
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bool CCState::CheckReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
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bool CCState::CheckReturn(const SmallVectorImpl<EVT> &OutTys,
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const SmallVectorImpl<ISD::ArgFlagsTy> &ArgsFlags,
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CCAssignFn Fn) {
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// Determine which register each value should be copied into.
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for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
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EVT VT = Outs[i].VT;
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ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
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for (unsigned i = 0, e = OutTys.size(); i != e; ++i) {
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EVT VT = OutTys[i];
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ISD::ArgFlagsTy ArgFlags = ArgsFlags[i];
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if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this))
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return false;
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}
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