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Revert 95130.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@95160 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2010-02-02 23:55:14 +00:00
parent 9d73d78f45
commit 022d9e1cef
26 changed files with 35 additions and 31 deletions
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2
include/llvm/Target/TargetLowering.h
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@ -1168,7 +1168,7 @@ public:
/// InVals array with legal-type return values from the call, and return /// InVals array with legal-type return values from the call, and return
/// the resulting token chain value. /// the resulting token chain value.
virtual SDValue virtual SDValue
LowerCall(SDValue Chain, SDValue Callee, const Type *RetTy, LowerCall(SDValue Chain, SDValue Callee,
CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, CallingConv::ID CallConv, bool isVarArg, bool &isTailCall,
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::OutputArg> &Outs,
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,

2
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
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@ -5735,7 +5735,7 @@ TargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy,
} }
SmallVector<SDValue, 4> InVals; SmallVector<SDValue, 4> InVals;
Chain = LowerCall(Chain, Callee, RetTy, CallConv, isVarArg, isTailCall, Chain = LowerCall(Chain, Callee, CallConv, isVarArg, isTailCall,
Outs, Ins, dl, DAG, InVals); Outs, Ins, dl, DAG, InVals);
// Verify that the target's LowerCall behaved as expected. // Verify that the target's LowerCall behaved as expected.

2
lib/Target/ARM/ARMISelLowering.cpp
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@ -895,7 +895,7 @@ void ARMTargetLowering::PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG,
/// ARMISD:CALL <- callseq_end chain. Also add input and output parameter /// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
/// nodes. /// nodes.
SDValue SDValue
ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee, const Type *RetTy, ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
CallingConv::ID CallConv, bool isVarArg, CallingConv::ID CallConv, bool isVarArg,
bool &isTailCall, bool &isTailCall,
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::OutputArg> &Outs,

2
lib/Target/ARM/ARMISelLowering.h
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@ -317,7 +317,7 @@ namespace llvm {
SmallVectorImpl<SDValue> &InVals); SmallVectorImpl<SDValue> &InVals);
virtual SDValue virtual SDValue
LowerCall(SDValue Chain, SDValue Callee, const Type *RetTy, LowerCall(SDValue Chain, SDValue Callee,
CallingConv::ID CallConv, bool isVarArg, CallingConv::ID CallConv, bool isVarArg,
bool &isTailCall, bool &isTailCall,
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::OutputArg> &Outs,

2
lib/Target/Alpha/AlphaISelLowering.cpp
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@ -219,7 +219,7 @@ static SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) {
#include "AlphaGenCallingConv.inc" #include "AlphaGenCallingConv.inc"
SDValue SDValue
AlphaTargetLowering::LowerCall(SDValue Chain, SDValue Callee, const Type *RetTy, AlphaTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
CallingConv::ID CallConv, bool isVarArg, CallingConv::ID CallConv, bool isVarArg,
bool &isTailCall, bool &isTailCall,
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::OutputArg> &Outs,

2
lib/Target/Alpha/AlphaISelLowering.h
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@ -120,7 +120,7 @@ namespace llvm {
SmallVectorImpl<SDValue> &InVals); SmallVectorImpl<SDValue> &InVals);
virtual SDValue virtual SDValue
LowerCall(SDValue Chain, SDValue Callee, const Type *RetTy, LowerCall(SDValue Chain, SDValue Callee,
CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, CallingConv::ID CallConv, bool isVarArg, bool &isTailCall,
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::OutputArg> &Outs,
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,

1
lib/Target/Blackfin/BlackfinISelLowering.cpp
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@ -272,7 +272,6 @@ BlackfinTargetLowering::LowerReturn(SDValue Chain,
SDValue SDValue
BlackfinTargetLowering::LowerCall(SDValue Chain, SDValue Callee, BlackfinTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
const Type *RetTy,
CallingConv::ID CallConv, bool isVarArg, CallingConv::ID CallConv, bool isVarArg,
bool &isTailCall, bool &isTailCall,
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::OutputArg> &Outs,

2
lib/Target/Blackfin/BlackfinISelLowering.h
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@ -63,7 +63,7 @@ namespace llvm {
DebugLoc dl, SelectionDAG &DAG, DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals); SmallVectorImpl<SDValue> &InVals);
virtual SDValue virtual SDValue
LowerCall(SDValue Chain, SDValue Callee, const Type *RetTy, LowerCall(SDValue Chain, SDValue Callee,
CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, CallingConv::ID CallConv, bool isVarArg, bool &isTailCall,
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::OutputArg> &Outs,
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,

2
lib/Target/CellSPU/SPUISelLowering.cpp
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@ -1138,7 +1138,7 @@ static SDNode *isLSAAddress(SDValue Op, SelectionDAG &DAG) {
} }
SDValue SDValue
SPUTargetLowering::LowerCall(SDValue Chain, SDValue Callee, const Type *RetTy, SPUTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
CallingConv::ID CallConv, bool isVarArg, CallingConv::ID CallConv, bool isVarArg,
bool &isTailCall, bool &isTailCall,
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::OutputArg> &Outs,

2
lib/Target/CellSPU/SPUISelLowering.h
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@ -156,7 +156,7 @@ namespace llvm {
SmallVectorImpl<SDValue> &InVals); SmallVectorImpl<SDValue> &InVals);
virtual SDValue virtual SDValue
LowerCall(SDValue Chain, SDValue Callee, const Type *RetTy, LowerCall(SDValue Chain, SDValue Callee,
CallingConv::ID CallConv, bool isVarArg, CallingConv::ID CallConv, bool isVarArg,
bool &isTailCall, bool &isTailCall,
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::OutputArg> &Outs,

2
lib/Target/MSP430/MSP430ISelLowering.cpp
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@ -271,7 +271,7 @@ MSP430TargetLowering::LowerFormalArguments(SDValue Chain,
} }
SDValue SDValue
MSP430TargetLowering::LowerCall(SDValue Chain, SDValue Callee,const Type *RetTy, MSP430TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
CallingConv::ID CallConv, bool isVarArg, CallingConv::ID CallConv, bool isVarArg,
bool &isTailCall, bool &isTailCall,
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::OutputArg> &Outs,

2
lib/Target/MSP430/MSP430ISelLowering.h
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@ -153,7 +153,7 @@ namespace llvm {
DebugLoc dl, SelectionDAG &DAG, DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals); SmallVectorImpl<SDValue> &InVals);
virtual SDValue virtual SDValue
LowerCall(SDValue Chain, SDValue Callee, const Type *RetTy, LowerCall(SDValue Chain, SDValue Callee,
CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, CallingConv::ID CallConv, bool isVarArg, bool &isTailCall,
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::OutputArg> &Outs,
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,

2
lib/Target/Mips/MipsISelLowering.cpp
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@ -684,7 +684,7 @@ static bool CC_MipsO32(unsigned ValNo, EVT ValVT,
/// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted. /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
/// TODO: isVarArg, isTailCall. /// TODO: isVarArg, isTailCall.
SDValue SDValue
MipsTargetLowering::LowerCall(SDValue Chain, SDValue Callee, const Type *RetTy, MipsTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
CallingConv::ID CallConv, bool isVarArg, CallingConv::ID CallConv, bool isVarArg,
bool &isTailCall, bool &isTailCall,
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::OutputArg> &Outs,

2
lib/Target/Mips/MipsISelLowering.h
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@ -116,7 +116,7 @@ namespace llvm {
SmallVectorImpl<SDValue> &InVals); SmallVectorImpl<SDValue> &InVals);
virtual SDValue virtual SDValue
LowerCall(SDValue Chain, SDValue Callee, const Type *RetTy, LowerCall(SDValue Chain, SDValue Callee,
CallingConv::ID CallConv, bool isVarArg, CallingConv::ID CallConv, bool isVarArg,
bool &isTailCall, bool &isTailCall,
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::OutputArg> &Outs,

2
lib/Target/PIC16/PIC16ISelLowering.cpp
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@ -1353,7 +1353,7 @@ GetDataAddress(DebugLoc dl, SDValue Callee, SDValue &Chain,
} }
SDValue SDValue
PIC16TargetLowering::LowerCall(SDValue Chain, SDValue Callee, const Type *RetTy, PIC16TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
CallingConv::ID CallConv, bool isVarArg, CallingConv::ID CallConv, bool isVarArg,
bool &isTailCall, bool &isTailCall,
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::OutputArg> &Outs,

2
lib/Target/PIC16/PIC16ISelLowering.h
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@ -142,7 +142,7 @@ namespace llvm {
SmallVectorImpl<SDValue> &InVals); SmallVectorImpl<SDValue> &InVals);
virtual SDValue virtual SDValue
LowerCall(SDValue Chain, SDValue Callee, const Type *RetTy, LowerCall(SDValue Chain, SDValue Callee,
CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, CallingConv::ID CallConv, bool isVarArg, bool &isTailCall,
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::OutputArg> &Outs,
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,

2
lib/Target/PowerPC/PPCISelLowering.cpp
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@ -2674,7 +2674,7 @@ PPCTargetLowering::FinishCall(CallingConv::ID CallConv, DebugLoc dl,
} }
SDValue SDValue
PPCTargetLowering::LowerCall(SDValue Chain, SDValue Callee, const Type *RetTy, PPCTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
CallingConv::ID CallConv, bool isVarArg, CallingConv::ID CallConv, bool isVarArg,
bool &isTailCall, bool &isTailCall,
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::OutputArg> &Outs,

2
lib/Target/PowerPC/PPCISelLowering.h
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@ -430,7 +430,7 @@ namespace llvm {
SmallVectorImpl<SDValue> &InVals); SmallVectorImpl<SDValue> &InVals);
virtual SDValue virtual SDValue
LowerCall(SDValue Chain, SDValue Callee, const Type *RetTy, LowerCall(SDValue Chain, SDValue Callee,
CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, CallingConv::ID CallConv, bool isVarArg, bool &isTailCall,
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::OutputArg> &Outs,
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,

2
lib/Target/Sparc/SparcISelLowering.cpp
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@ -250,7 +250,7 @@ SparcTargetLowering::LowerFormalArguments(SDValue Chain,
} }
SDValue SDValue
SparcTargetLowering::LowerCall(SDValue Chain, SDValue Callee, const Type *RetTy, SparcTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
CallingConv::ID CallConv, bool isVarArg, CallingConv::ID CallConv, bool isVarArg,
bool &isTailCall, bool &isTailCall,
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::OutputArg> &Outs,

2
lib/Target/Sparc/SparcISelLowering.h
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@ -85,7 +85,7 @@ namespace llvm {
SmallVectorImpl<SDValue> &InVals); SmallVectorImpl<SDValue> &InVals);
virtual SDValue virtual SDValue
LowerCall(SDValue Chain, SDValue Callee, const Type *RetTy, LowerCall(SDValue Chain, SDValue Callee,
CallingConv::ID CallConv, bool isVarArg, CallingConv::ID CallConv, bool isVarArg,
bool &isTailCall, bool &isTailCall,
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::OutputArg> &Outs,

1
lib/Target/SystemZ/SystemZISelLowering.cpp
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@ -249,7 +249,6 @@ SystemZTargetLowering::LowerFormalArguments(SDValue Chain,
SDValue SDValue
SystemZTargetLowering::LowerCall(SDValue Chain, SDValue Callee, SystemZTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
const Type *RetTy,
CallingConv::ID CallConv, bool isVarArg, CallingConv::ID CallConv, bool isVarArg,
bool &isTailCall, bool &isTailCall,
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::OutputArg> &Outs,

2
lib/Target/SystemZ/SystemZISelLowering.h
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@ -124,7 +124,7 @@ namespace llvm {
DebugLoc dl, SelectionDAG &DAG, DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals); SmallVectorImpl<SDValue> &InVals);
virtual SDValue virtual SDValue
LowerCall(SDValue Chain, SDValue Callee, const Type *RetTy, LowerCall(SDValue Chain, SDValue Callee,
CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, CallingConv::ID CallConv, bool isVarArg, bool &isTailCall,
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::OutputArg> &Outs,
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,

16
lib/Target/X86/X86ISelLowering.cpp
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@ -1778,7 +1778,7 @@ EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
} }
SDValue SDValue
X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee, const Type *RetTy, X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
CallingConv::ID CallConv, bool isVarArg, CallingConv::ID CallConv, bool isVarArg,
bool &isTailCall, bool &isTailCall,
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::OutputArg> &Outs,
@ -1791,8 +1791,8 @@ X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee, const Type *RetTy,
if (isTailCall) if (isTailCall)
// Check if it's really possible to do a tail call. // Check if it's really possible to do a tail call.
isTailCall = IsEligibleForTailCallOptimization(Callee, RetTy, CallConv, isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg,
isVarArg, Outs, Ins, DAG); Outs, Ins, DAG);
assert(!(isVarArg && CallConv == CallingConv::Fast) && assert(!(isVarArg && CallConv == CallingConv::Fast) &&
"Var args not supported with calling convention fastcc"); "Var args not supported with calling convention fastcc");
@ -2247,7 +2247,6 @@ unsigned X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize,
/// optimization should implement this function. /// optimization should implement this function.
bool bool
X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee, X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
const Type *RetTy,
CallingConv::ID CalleeCC, CallingConv::ID CalleeCC,
bool isVarArg, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::OutputArg> &Outs,
@ -2329,7 +2328,14 @@ X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
return true; return true;
// If the return types match, then it's safe. // If the return types match, then it's safe.
return CallerRetTy == RetTy; // Don't tail call optimize recursive call.
GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee);
if (!G) return false; // FIXME: common external symbols?
if (const Function *CalleeF = dyn_cast<Function>(G->getGlobal())) {
const Type *CalleeRetTy = CalleeF->getReturnType();
return CallerRetTy == CalleeRetTy;
}
return false;
} }
FastISel * FastISel *

4
lib/Target/X86/X86ISelLowering.h
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@ -627,7 +627,7 @@ namespace llvm {
/// IsEligibleForTailCallOptimization - Check whether the call is eligible /// IsEligibleForTailCallOptimization - Check whether the call is eligible
/// for tail call optimization. Targets which want to do tail call /// for tail call optimization. Targets which want to do tail call
/// optimization should implement this function. /// optimization should implement this function.
bool IsEligibleForTailCallOptimization(SDValue Callee, const Type *RetTy, bool IsEligibleForTailCallOptimization(SDValue Callee,
CallingConv::ID CalleeCC, CallingConv::ID CalleeCC,
bool isVarArg, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::OutputArg> &Outs,
@ -707,7 +707,7 @@ namespace llvm {
DebugLoc dl, SelectionDAG &DAG, DebugLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals); SmallVectorImpl<SDValue> &InVals);
virtual SDValue virtual SDValue
LowerCall(SDValue Chain, SDValue Callee, const Type *RetTy, LowerCall(SDValue Chain, SDValue Callee,
CallingConv::ID CallConv, bool isVarArg, bool &isTailCall, CallingConv::ID CallConv, bool isVarArg, bool &isTailCall,
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::OutputArg> &Outs,
const SmallVectorImpl<ISD::InputArg> &Ins, const SmallVectorImpl<ISD::InputArg> &Ins,

2
lib/Target/XCore/XCoreISelLowering.cpp
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@ -609,7 +609,7 @@ SDValue XCoreTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) {
/// XCore call implementation /// XCore call implementation
SDValue SDValue
XCoreTargetLowering::LowerCall(SDValue Chain, SDValue Callee, const Type *RetTy, XCoreTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
CallingConv::ID CallConv, bool isVarArg, CallingConv::ID CallConv, bool isVarArg,
bool &isTailCall, bool &isTailCall,
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::OutputArg> &Outs,

2
lib/Target/XCore/XCoreISelLowering.h
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@ -147,7 +147,7 @@ namespace llvm {
SmallVectorImpl<SDValue> &InVals); SmallVectorImpl<SDValue> &InVals);
virtual SDValue virtual SDValue
LowerCall(SDValue Chain, SDValue Callee, const Type *RetTy, LowerCall(SDValue Chain, SDValue Callee,
CallingConv::ID CallConv, bool isVarArg, CallingConv::ID CallConv, bool isVarArg,
bool &isTailCall, bool &isTailCall,
const SmallVectorImpl<ISD::OutputArg> &Outs, const SmallVectorImpl<ISD::OutputArg> &Outs,