From 02327fefd8a4b7d9f4dc90e066ba70b1d6253c27 Mon Sep 17 00:00:00 2001 From: Hal Finkel Date: Sat, 23 Mar 2013 19:36:47 +0000 Subject: [PATCH] Cleanup some unused reg. scavenger parameters in PPCRegisterInfo These spilling functions will eventually make use of the register scavenger, however, they'll do so by taking advantage of PEI's virtual-register-based delayed scavenging mechanism. As a result, these function parameters will not be used, and can be removed. No functionality change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177827 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/PowerPC/PPCRegisterInfo.cpp | 33 ++++++++------------------ lib/Target/PowerPC/PPCRegisterInfo.h | 19 +++++++-------- 2 files changed, 19 insertions(+), 33 deletions(-) diff --git a/lib/Target/PowerPC/PPCRegisterInfo.cpp b/lib/Target/PowerPC/PPCRegisterInfo.cpp index 75e20e4a269..e3701e0f158 100644 --- a/lib/Target/PowerPC/PPCRegisterInfo.cpp +++ b/lib/Target/PowerPC/PPCRegisterInfo.cpp @@ -203,8 +203,7 @@ PPCRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, /// stwxu R0, SP, Rnegsize ; add and update the SP with the negated size /// addi Rnew, SP, \#maxCalFrameSize ; get the top of the allocation /// -void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II, - int SPAdj, RegScavenger *RS) const { +void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II) const { // Get the instruction. MachineInstr &MI = *II; // Get the instruction's basic block. @@ -300,8 +299,7 @@ void PPCRegisterInfo::lowerDynamicAlloc(MachineBasicBlock::iterator II, /// stw rA, FI ; Store rA to the frame. /// void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II, - unsigned FrameIndex, int SPAdj, - RegScavenger *RS) const { + unsigned FrameIndex) const { // Get the instruction. MachineInstr &MI = *II; // ; SPILL_CR , // Get the instruction's basic block. @@ -311,8 +309,6 @@ void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II, // FIXME: Once LLVM supports creating virtual registers here, or the register // scavenger can return multiple registers, stop using reserved registers // here. - (void) SPAdj; - (void) RS; bool LP64 = Subtarget.isPPC64(); unsigned Reg = LP64 ? PPC::X0 : PPC::R0; @@ -342,8 +338,7 @@ void PPCRegisterInfo::lowerCRSpilling(MachineBasicBlock::iterator II, } void PPCRegisterInfo::lowerCRRestore(MachineBasicBlock::iterator II, - unsigned FrameIndex, int SPAdj, - RegScavenger *RS) const { + unsigned FrameIndex) const { // Get the instruction. MachineInstr &MI = *II; // ; = RESTORE_CR // Get the instruction's basic block. @@ -353,8 +348,6 @@ void PPCRegisterInfo::lowerCRRestore(MachineBasicBlock::iterator II, // FIXME: Once LLVM supports creating virtual registers here, or the register // scavenger can return multiple registers, stop using reserved registers // here. - (void) SPAdj; - (void) RS; bool LP64 = Subtarget.isPPC64(); unsigned Reg = LP64 ? PPC::X0 : PPC::R0; @@ -383,8 +376,7 @@ void PPCRegisterInfo::lowerCRRestore(MachineBasicBlock::iterator II, } void PPCRegisterInfo::lowerVRSAVESpilling(MachineBasicBlock::iterator II, - unsigned FrameIndex, int SPAdj, - RegScavenger *RS) const { + unsigned FrameIndex) const { // Get the instruction. MachineInstr &MI = *II; // ; SPILL_VRSAVE , // Get the instruction's basic block. @@ -394,8 +386,6 @@ void PPCRegisterInfo::lowerVRSAVESpilling(MachineBasicBlock::iterator II, // FIXME: Once LLVM supports creating virtual registers here, or the register // scavenger can return multiple registers, stop using reserved registers // here. - (void) SPAdj; - (void) RS; unsigned Reg = PPC::R0; unsigned SrcReg = MI.getOperand(0).getReg(); @@ -412,8 +402,7 @@ void PPCRegisterInfo::lowerVRSAVESpilling(MachineBasicBlock::iterator II, } void PPCRegisterInfo::lowerVRSAVERestore(MachineBasicBlock::iterator II, - unsigned FrameIndex, int SPAdj, - RegScavenger *RS) const { + unsigned FrameIndex) const { // Get the instruction. MachineInstr &MI = *II; // ; = RESTORE_VRSAVE // Get the instruction's basic block. @@ -423,8 +412,6 @@ void PPCRegisterInfo::lowerVRSAVERestore(MachineBasicBlock::iterator II, // FIXME: Once LLVM supports creating virtual registers here, or the register // scavenger can return multiple registers, stop using reserved registers // here. - (void) SPAdj; - (void) RS; unsigned Reg = PPC::R0; unsigned DestReg = MI.getOperand(0).getReg(); @@ -497,22 +484,22 @@ PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, // Special case for dynamic alloca. if (FPSI && FrameIndex == FPSI && (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) { - lowerDynamicAlloc(II, SPAdj, RS); + lowerDynamicAlloc(II); return; } // Special case for pseudo-ops SPILL_CR and RESTORE_CR, etc. if (OpC == PPC::SPILL_CR) { - lowerCRSpilling(II, FrameIndex, SPAdj, RS); + lowerCRSpilling(II, FrameIndex); return; } else if (OpC == PPC::RESTORE_CR) { - lowerCRRestore(II, FrameIndex, SPAdj, RS); + lowerCRRestore(II, FrameIndex); return; } else if (OpC == PPC::SPILL_VRSAVE) { - lowerVRSAVESpilling(II, FrameIndex, SPAdj, RS); + lowerVRSAVESpilling(II, FrameIndex); return; } else if (OpC == PPC::RESTORE_VRSAVE) { - lowerVRSAVERestore(II, FrameIndex, SPAdj, RS); + lowerVRSAVERestore(II, FrameIndex); return; } diff --git a/lib/Target/PowerPC/PPCRegisterInfo.h b/lib/Target/PowerPC/PPCRegisterInfo.h index ba0fb48b851..231bcd16846 100644 --- a/lib/Target/PowerPC/PPCRegisterInfo.h +++ b/lib/Target/PowerPC/PPCRegisterInfo.h @@ -61,16 +61,15 @@ public: return true; } - void lowerDynamicAlloc(MachineBasicBlock::iterator II, - int SPAdj, RegScavenger *RS) const; - void lowerCRSpilling(MachineBasicBlock::iterator II, unsigned FrameIndex, - int SPAdj, RegScavenger *RS) const; - void lowerCRRestore(MachineBasicBlock::iterator II, unsigned FrameIndex, - int SPAdj, RegScavenger *RS) const; - void lowerVRSAVESpilling(MachineBasicBlock::iterator II, unsigned FrameIndex, - int SPAdj, RegScavenger *RS) const; - void lowerVRSAVERestore(MachineBasicBlock::iterator II, unsigned FrameIndex, - int SPAdj, RegScavenger *RS) const; + void lowerDynamicAlloc(MachineBasicBlock::iterator II) const; + void lowerCRSpilling(MachineBasicBlock::iterator II, + unsigned FrameIndex) const; + void lowerCRRestore(MachineBasicBlock::iterator II, + unsigned FrameIndex) const; + void lowerVRSAVESpilling(MachineBasicBlock::iterator II, + unsigned FrameIndex) const; + void lowerVRSAVERestore(MachineBasicBlock::iterator II, + unsigned FrameIndex) const; bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg, int &FrameIdx) const;