From 025c1cefca00f262452c8c42717a4047b1836cd2 Mon Sep 17 00:00:00 2001
From: Hal Finkel <hfinkel@anl.gov>
Date: Thu, 6 Mar 2014 00:23:33 +0000
Subject: [PATCH] When using CR bit registers on PPC32, handle the i1 vaarg
 case

When copying an i1 value into a GPR for a vaarg call, we need to explicitly
zero-extend the i1 value (otherwise an invalid CRBIT -> GPR copy will be
generated).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203041 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/PowerPC/PPCISelLowering.cpp |  3 +++
 test/CodeGen/PowerPC/ppc32-i1-vaarg.ll | 15 +++++++++++++++
 2 files changed, 18 insertions(+)
 create mode 100644 test/CodeGen/PowerPC/ppc32-i1-vaarg.ll

diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp
index 05e74fb049f..dce6051b182 100644
--- a/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -3773,6 +3773,9 @@ PPCTargetLowering::LowerCall_32SVR4(SDValue Chain, SDValue Callee,
     }
 
     if (VA.isRegLoc()) {
+      if (Arg.getValueType() == MVT::i1)
+        Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Arg);
+
       seenFloatArg |= VA.getLocVT().isFloatingPoint();
       // Put argument in a physical register.
       RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
diff --git a/test/CodeGen/PowerPC/ppc32-i1-vaarg.ll b/test/CodeGen/PowerPC/ppc32-i1-vaarg.ll
new file mode 100644
index 00000000000..096ea384f05
--- /dev/null
+++ b/test/CodeGen/PowerPC/ppc32-i1-vaarg.ll
@@ -0,0 +1,15 @@
+; RUN: llc < %s -march=ppc32 -mcpu=ppc32 | FileCheck %s
+target triple = "powerpc-unknown-linux-gnu"
+
+declare void @printf(i8*, ...)
+
+define void @main() {
+  call void (i8*, ...)* @printf(i8* undef, i1 false)
+  ret void
+}
+
+; CHECK-LABEL: @main
+; CHECK-DAG li 4, 0
+; CHECK-DAG: crxor 6, 6, 6
+; CHECK: bl printf
+