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Merging r226190:

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r226190 | marek.olsak | 2015-01-15 13:43:01 -0500 (Thu, 15 Jan 2015) | 2 lines

R600/SI: Use 64-bit encoding by default for opcodes that are VOP3-only on VI

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@226719 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tom Stellard committed 2015-01-21 22:44:40 +00:00
1 parent 2a56d539b3
commit 028c9e7906
4 files changed
+37 -40
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lib/Target/R600/SIInstrInfo.cpp
+3 -3
View File
@@ -615,7 +615,7 @@ unsigned SIInstrInfo::calculateLDSSpillAddress(MachineBasicBlock &MBB,
.addImm(-1)
.addImm(0);
BuildMI(Entry, Insert, DL, get(AMDGPU::V_MBCNT_HI_U32_B32_e32),
BuildMI(Entry, Insert, DL, get(AMDGPU::V_MBCNT_HI_U32_B32_e64),
TIDReg)
.addImm(-1)
.addReg(TIDReg);
@@ -1291,7 +1291,7 @@ unsigned SIInstrInfo::getVALUOp(const MachineInstr &MI) {
case AMDGPU::S_LOAD_DWORDX2_SGPR: return AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64;
case AMDGPU::S_LOAD_DWORDX4_IMM:
case AMDGPU::S_LOAD_DWORDX4_SGPR: return AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64;
case AMDGPU::S_BCNT1_I32_B32: return AMDGPU::V_BCNT_U32_B32_e32;
case AMDGPU::S_BCNT1_I32_B32: return AMDGPU::V_BCNT_U32_B32_e64;
case AMDGPU::S_FF1_I32_B32: return AMDGPU::V_FFBL_B32_e32;
case AMDGPU::S_FLBIT_I32_B32: return AMDGPU::V_FFBH_U32_e32;
}
@@ -2282,7 +2282,7 @@ void SIInstrInfo::splitScalar64BitBCNT(SmallVectorImpl<MachineInstr *> &Worklist
MachineOperand &Dest = Inst->getOperand(0);
MachineOperand &Src = Inst->getOperand(1);
const MCInstrDesc &InstDesc = get(AMDGPU::V_BCNT_U32_B32_e32);
const MCInstrDesc &InstDesc = get(AMDGPU::V_BCNT_U32_B32_e64);
const TargetRegisterClass *SrcRC = Src.isReg() ?
MRI.getRegClass(Src.getReg()) :
&AMDGPU::SGPR_32RegClass;
lib/Target/R600/SIInstructions.td
+1 -1
View File
@@ -2735,7 +2735,7 @@ let Predicates = [isSICI] in {
def : Pat <
(int_SI_tid),
(V_MBCNT_HI_U32_B32_e32 0xffffffff,
(V_MBCNT_HI_U32_B32_e64 0xffffffff,
(V_MBCNT_LO_U32_B32_e64 0xffffffff, 0))
>;
test/CodeGen/R600/ctpop.ll
+32 -34
View File
@@ -24,8 +24,7 @@ define void @s_ctpop_i32(i32 addrspace(1)* noalias %out, i32 %val) nounwind {
; XXX - Why 0 in register?
; FUNC-LABEL: {{^}}v_ctpop_i32:
; SI: buffer_load_dword [[VAL:v[0-9]+]],
; SI: v_mov_b32_e32 [[VZERO:v[0-9]+]], 0
; SI: v_bcnt_u32_b32_e32 [[RESULT:v[0-9]+]], [[VAL]], [[VZERO]]
; SI: v_bcnt_u32_b32_e64 [[RESULT:v[0-9]+]], [[VAL]], 0
; SI: buffer_store_dword [[RESULT]],
; SI: s_endpgm
@@ -40,8 +39,7 @@ define void @v_ctpop_i32(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noali
; FUNC-LABEL: {{^}}v_ctpop_add_chain_i32:
; SI: buffer_load_dword [[VAL0:v[0-9]+]],
; SI: buffer_load_dword [[VAL1:v[0-9]+]],
; SI: v_mov_b32_e32 [[VZERO:v[0-9]+]], 0
; SI: v_bcnt_u32_b32_e32 [[MIDRESULT:v[0-9]+]], [[VAL1]], [[VZERO]]
; SI: v_bcnt_u32_b32_e64 [[MIDRESULT:v[0-9]+]], [[VAL1]], 0
; SI-NEXT: v_bcnt_u32_b32_e32 [[RESULT:v[0-9]+]], [[VAL0]], [[MIDRESULT]]
; SI: buffer_store_dword [[RESULT]],
; SI: s_endpgm
@@ -73,8 +71,8 @@ define void @v_ctpop_add_sgpr_i32(i32 addrspace(1)* noalias %out, i32 addrspace(
}
; FUNC-LABEL: {{^}}v_ctpop_v2i32:
; SI: v_bcnt_u32_b32_e32
; SI: v_bcnt_u32_b32_e32
; SI: v_bcnt_u32_b32_e64
; SI: v_bcnt_u32_b32_e64
; SI: s_endpgm
; EG: BCNT_INT
@@ -87,10 +85,10 @@ define void @v_ctpop_v2i32(<2 x i32> addrspace(1)* noalias %out, <2 x i32> addrs
}
; FUNC-LABEL: {{^}}v_ctpop_v4i32:
; SI: v_bcnt_u32_b32_e32
; SI: v_bcnt_u32_b32_e32
; SI: v_bcnt_u32_b32_e32
; SI: v_bcnt_u32_b32_e32
; SI: v_bcnt_u32_b32_e64
; SI: v_bcnt_u32_b32_e64
; SI: v_bcnt_u32_b32_e64
; SI: v_bcnt_u32_b32_e64
; SI: s_endpgm
; EG: BCNT_INT
@@ -105,14 +103,14 @@ define void @v_ctpop_v4i32(<4 x i32> addrspace(1)* noalias %out, <4 x i32> addrs
}
; FUNC-LABEL: {{^}}v_ctpop_v8i32:
; SI: v_bcnt_u32_b32_e32
; SI: v_bcnt_u32_b32_e32
; SI: v_bcnt_u32_b32_e32
; SI: v_bcnt_u32_b32_e32
; SI: v_bcnt_u32_b32_e32
; SI: v_bcnt_u32_b32_e32
; SI: v_bcnt_u32_b32_e32
; SI: v_bcnt_u32_b32_e32
; SI: v_bcnt_u32_b32_e64
; SI: v_bcnt_u32_b32_e64
; SI: v_bcnt_u32_b32_e64
; SI: v_bcnt_u32_b32_e64
; SI: v_bcnt_u32_b32_e64
; SI: v_bcnt_u32_b32_e64
; SI: v_bcnt_u32_b32_e64
; SI: v_bcnt_u32_b32_e64
; SI: s_endpgm
; EG: BCNT_INT
@@ -131,22 +129,22 @@ define void @v_ctpop_v8i32(<8 x i32> addrspace(1)* noalias %out, <8 x i32> addrs
}
; FUNC-LABEL: {{^}}v_ctpop_v16i32:
; SI: v_bcnt_u32_b32_e32
; SI: v_bcnt_u32_b32_e32
; SI: v_bcnt_u32_b32_e32
; SI: v_bcnt_u32_b32_e32
; SI: v_bcnt_u32_b32_e32
; SI: v_bcnt_u32_b32_e32
; SI: v_bcnt_u32_b32_e32
; SI: v_bcnt_u32_b32_e32
; SI: v_bcnt_u32_b32_e32
; SI: v_bcnt_u32_b32_e32
; SI: v_bcnt_u32_b32_e32
; SI: v_bcnt_u32_b32_e32
; SI: v_bcnt_u32_b32_e32
; SI: v_bcnt_u32_b32_e32
; SI: v_bcnt_u32_b32_e32
; SI: v_bcnt_u32_b32_e32
; SI: v_bcnt_u32_b32_e64
; SI: v_bcnt_u32_b32_e64
; SI: v_bcnt_u32_b32_e64
; SI: v_bcnt_u32_b32_e64
; SI: v_bcnt_u32_b32_e64
; SI: v_bcnt_u32_b32_e64
; SI: v_bcnt_u32_b32_e64
; SI: v_bcnt_u32_b32_e64
; SI: v_bcnt_u32_b32_e64
; SI: v_bcnt_u32_b32_e64
; SI: v_bcnt_u32_b32_e64
; SI: v_bcnt_u32_b32_e64
; SI: v_bcnt_u32_b32_e64
; SI: v_bcnt_u32_b32_e64
; SI: v_bcnt_u32_b32_e64
; SI: v_bcnt_u32_b32_e64
; SI: s_endpgm
; EG: BCNT_INT
test/CodeGen/R600/ctpop64.ll
+1 -2
View File
@@ -21,8 +21,7 @@ define void @s_ctpop_i64(i32 addrspace(1)* noalias %out, i64 %val) nounwind {
; FUNC-LABEL: {{^}}v_ctpop_i64:
; SI: buffer_load_dwordx2 v{{\[}}[[LOVAL:[0-9]+]]:[[HIVAL:[0-9]+]]{{\]}},
; SI: v_mov_b32_e32 [[VZERO:v[0-9]+]], 0
; SI: v_bcnt_u32_b32_e32 [[MIDRESULT:v[0-9]+]], v[[LOVAL]], [[VZERO]]
; SI: v_bcnt_u32_b32_e64 [[MIDRESULT:v[0-9]+]], v[[LOVAL]], 0
; SI-NEXT: v_bcnt_u32_b32_e32 [[RESULT:v[0-9]+]], v[[HIVAL]], [[MIDRESULT]]
; SI: buffer_store_dword [[RESULT]],
; SI: s_endpgm