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Fix for PR1540: Specify F0, F1 are sub-registers of D0, etc.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@39843 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
2007-07-13 23:55:50 +00:00
parent a08971559d
commit 03494d7c8f
1 changed files with 2 additions and 2 deletions
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4
lib/Target/Sparc/SparcRegisterInfo.td
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@@ -26,9 +26,9 @@ class Rf<bits<5> num, string n> : SparcReg<n> {
let Num = num;
}
// Rd - Slots in the FP register file for 64-bit floating-point values.
class Rd<bits<5> num, string n, list<Register> aliases> : SparcReg<n> {
class Rd<bits<5> num, string n, list<Register> subregs> : SparcReg<n> {
let Num = num;
let Aliases = aliases;
let SubRegs = subregs;
}
// Integer registers