mirror of
https://github.com/c64scene-ar/llvm-6502.git
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Simple refactoring of SSE4.1 instructions, making room for the AVX forms
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107540 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bruno Cardoso Lopes
parent
ff23535df6
commit
03560600b4
@ -3904,7 +3904,7 @@ def : Pat<(store (v16i8 VR128:$src), addr:$dst),
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(MOVUPSmr addr:$dst, VR128:$src)>;
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//===----------------------------------------------------------------------===//
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// SSE4.1 Instructions
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// SSE4.1 - Misc Instructions
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//===----------------------------------------------------------------------===//
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multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd,
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@ -3948,56 +3948,61 @@ multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd,
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OpSize;
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}
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let Constraints = "$src1 = $dst" in {
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multiclass sse41_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
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string OpcodeStr,
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Intrinsic F32Int,
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Intrinsic F64Int> {
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Intrinsic F64Int, bit Is2Addr = 1> {
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// Intrinsic operation, reg.
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def SSr_Int : SS4AIi8<opcss, MRMSrcReg,
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(outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
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!strconcat(OpcodeStr,
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"ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
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[(set VR128:$dst,
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(F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
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OpSize;
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(outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
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!if(Is2Addr,
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!strconcat(OpcodeStr,
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"ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
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!strconcat(OpcodeStr,
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"ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
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[(set VR128:$dst, (F32Int VR128:$src1, VR128:$src2, imm:$src3))]>,
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OpSize;
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// Intrinsic operation, mem.
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def SSm_Int : SS4AIi8<opcss, MRMSrcMem,
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(outs VR128:$dst),
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(ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
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!strconcat(OpcodeStr,
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"ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
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[(set VR128:$dst,
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(F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
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OpSize;
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(outs VR128:$dst), (ins VR128:$src1, ssmem:$src2, i32i8imm:$src3),
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!if(Is2Addr,
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!strconcat(OpcodeStr,
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"ss\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
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!strconcat(OpcodeStr,
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"ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
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[(set VR128:$dst,
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(F32Int VR128:$src1, sse_load_f32:$src2, imm:$src3))]>,
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OpSize;
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// Intrinsic operation, reg.
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def SDr_Int : SS4AIi8<opcsd, MRMSrcReg,
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(outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
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!strconcat(OpcodeStr,
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"sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
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[(set VR128:$dst,
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(F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
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OpSize;
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(outs VR128:$dst), (ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
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!if(Is2Addr,
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!strconcat(OpcodeStr,
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"sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
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!strconcat(OpcodeStr,
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"sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
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[(set VR128:$dst, (F64Int VR128:$src1, VR128:$src2, imm:$src3))]>,
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OpSize;
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// Intrinsic operation, mem.
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def SDm_Int : SS4AIi8<opcsd, MRMSrcMem,
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(outs VR128:$dst),
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(ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
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!strconcat(OpcodeStr,
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"sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
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[(set VR128:$dst,
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(F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
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OpSize;
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}
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(outs VR128:$dst), (ins VR128:$src1, sdmem:$src2, i32i8imm:$src3),
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!if(Is2Addr,
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!strconcat(OpcodeStr,
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"sd\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
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!strconcat(OpcodeStr,
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"sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
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[(set VR128:$dst,
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(F64Int VR128:$src1, sse_load_f64:$src2, imm:$src3))]>,
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OpSize;
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}
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// FP round - roundss, roundps, roundsd, roundpd
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defm ROUND : sse41_fp_unop_rm<0x08, 0x09, "round",
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int_x86_sse41_round_ps, int_x86_sse41_round_pd>;
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let Constraints = "$src1 = $dst" in
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defm ROUND : sse41_fp_binop_rm<0x0A, 0x0B, "round",
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int_x86_sse41_round_ss, int_x86_sse41_round_sd>;
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@ -4020,145 +4025,106 @@ defm PHMINPOSUW : SS41I_unop_rm_int_v16 <0x41, "phminposuw",
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int_x86_sse41_phminposuw>;
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/// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
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let Constraints = "$src1 = $dst" in {
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multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
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Intrinsic IntId128, bit Commutable = 0> {
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def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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[(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
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OpSize {
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let isCommutable = Commutable;
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}
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def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, i128mem:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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[(set VR128:$dst,
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(IntId128 VR128:$src1,
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(bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
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}
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multiclass SS41I_binop_rm_int<bits<8> opc, string OpcodeStr,
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Intrinsic IntId128, bit Is2Addr = 1> {
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let isCommutable = 1 in
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def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2),
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!if(Is2Addr,
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
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[(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>, OpSize;
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def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, i128mem:$src2),
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!if(Is2Addr,
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
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[(set VR128:$dst,
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(IntId128 VR128:$src1,
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(bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
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}
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defm PCMPEQQ : SS41I_binop_rm_int<0x29, "pcmpeqq",
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int_x86_sse41_pcmpeqq, 1>;
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defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw",
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int_x86_sse41_packusdw, 0>;
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defm PMINSB : SS41I_binop_rm_int<0x38, "pminsb",
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int_x86_sse41_pminsb, 1>;
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defm PMINSD : SS41I_binop_rm_int<0x39, "pminsd",
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int_x86_sse41_pminsd, 1>;
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defm PMINUD : SS41I_binop_rm_int<0x3B, "pminud",
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int_x86_sse41_pminud, 1>;
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defm PMINUW : SS41I_binop_rm_int<0x3A, "pminuw",
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int_x86_sse41_pminuw, 1>;
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defm PMAXSB : SS41I_binop_rm_int<0x3C, "pmaxsb",
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int_x86_sse41_pmaxsb, 1>;
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defm PMAXSD : SS41I_binop_rm_int<0x3D, "pmaxsd",
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int_x86_sse41_pmaxsd, 1>;
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defm PMAXUD : SS41I_binop_rm_int<0x3F, "pmaxud",
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int_x86_sse41_pmaxud, 1>;
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defm PMAXUW : SS41I_binop_rm_int<0x3E, "pmaxuw",
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int_x86_sse41_pmaxuw, 1>;
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defm PMULDQ : SS41I_binop_rm_int<0x28, "pmuldq", int_x86_sse41_pmuldq, 1>;
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let Constraints = "$src1 = $dst" in {
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let isCommutable = 0 in
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defm PACKUSDW : SS41I_binop_rm_int<0x2B, "packusdw", int_x86_sse41_packusdw>;
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defm PCMPEQQ : SS41I_binop_rm_int<0x29, "pcmpeqq", int_x86_sse41_pcmpeqq>;
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defm PMINSB : SS41I_binop_rm_int<0x38, "pminsb", int_x86_sse41_pminsb>;
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defm PMINSD : SS41I_binop_rm_int<0x39, "pminsd", int_x86_sse41_pminsd>;
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defm PMINUD : SS41I_binop_rm_int<0x3B, "pminud", int_x86_sse41_pminud>;
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defm PMINUW : SS41I_binop_rm_int<0x3A, "pminuw", int_x86_sse41_pminuw>;
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defm PMAXSB : SS41I_binop_rm_int<0x3C, "pmaxsb", int_x86_sse41_pmaxsb>;
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defm PMAXSD : SS41I_binop_rm_int<0x3D, "pmaxsd", int_x86_sse41_pmaxsd>;
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defm PMAXUD : SS41I_binop_rm_int<0x3F, "pmaxud", int_x86_sse41_pmaxud>;
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defm PMAXUW : SS41I_binop_rm_int<0x3E, "pmaxuw", int_x86_sse41_pmaxuw>;
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defm PMULDQ : SS41I_binop_rm_int<0x28, "pmuldq", int_x86_sse41_pmuldq>;
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}
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def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, VR128:$src2)),
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(PCMPEQQrr VR128:$src1, VR128:$src2)>;
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def : Pat<(v2i64 (X86pcmpeqq VR128:$src1, (memop addr:$src2))),
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(PCMPEQQrm VR128:$src1, addr:$src2)>;
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/// SS41I_binop_rm_int - Simple SSE 4.1 binary operator
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let Constraints = "$src1 = $dst" in {
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multiclass SS41I_binop_patint<bits<8> opc, string OpcodeStr, ValueType OpVT,
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SDNode OpNode, Intrinsic IntId128,
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bit Commutable = 0> {
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def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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[(set VR128:$dst, (OpNode (OpVT VR128:$src1),
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VR128:$src2))]>, OpSize {
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let isCommutable = Commutable;
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}
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def rr_int : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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[(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
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OpSize {
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let isCommutable = Commutable;
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}
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def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, i128mem:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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[(set VR128:$dst,
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(OpVT (OpNode VR128:$src1, (memop addr:$src2))))]>, OpSize;
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def rm_int : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, i128mem:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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[(set VR128:$dst,
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(IntId128 VR128:$src1, (memop addr:$src2)))]>,
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OpSize;
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}
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}
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/// SS48I_binop_rm - Simple SSE41 binary operator.
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let Constraints = "$src1 = $dst" in {
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multiclass SS48I_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
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ValueType OpVT, bit Commutable = 0> {
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ValueType OpVT, bit Is2Addr = 1> {
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let isCommutable = 1 in
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def rr : SS48I<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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[(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]>,
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OpSize {
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let isCommutable = Commutable;
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}
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(ins VR128:$src1, VR128:$src2),
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!if(Is2Addr,
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
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[(set VR128:$dst, (OpVT (OpNode VR128:$src1, VR128:$src2)))]>,
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OpSize;
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def rm : SS48I<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, i128mem:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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[(set VR128:$dst, (OpNode VR128:$src1,
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(ins VR128:$src1, i128mem:$src2),
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!if(Is2Addr,
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
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[(set VR128:$dst, (OpNode VR128:$src1,
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(bc_v4i32 (memopv2i64 addr:$src2))))]>,
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OpSize;
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}
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OpSize;
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}
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defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32, 1>;
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let Constraints = "$src1 = $dst" in
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defm PMULLD : SS48I_binop_rm<0x40, "pmulld", mul, v4i32>;
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/// SS41I_binop_rmi_int - SSE 4.1 binary operator with 8-bit immediate
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let Constraints = "$src1 = $dst" in {
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multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
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Intrinsic IntId128, bit Commutable = 0> {
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def rri : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
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[(set VR128:$dst,
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(IntId128 VR128:$src1, VR128:$src2, imm:$src3))]>,
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OpSize {
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let isCommutable = Commutable;
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}
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def rmi : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, i128mem:$src2, i32i8imm:$src3),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
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[(set VR128:$dst,
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(IntId128 VR128:$src1,
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(bitconvert (memopv16i8 addr:$src2)), imm:$src3))]>,
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OpSize;
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}
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multiclass SS41I_binop_rmi_int<bits<8> opc, string OpcodeStr,
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Intrinsic IntId128, bit Is2Addr = 1> {
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let isCommutable = 1 in
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def rri : SS4AIi8<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2, i32i8imm:$src3),
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!if(Is2Addr,
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
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[(set VR128:$dst,
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(IntId128 VR128:$src1, VR128:$src2, imm:$src3))]>,
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OpSize;
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def rmi : SS4AIi8<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, i128mem:$src2, i32i8imm:$src3),
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!if(Is2Addr,
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $dst|$dst, $src2, $src3}"),
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!strconcat(OpcodeStr,
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"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}")),
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[(set VR128:$dst,
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(IntId128 VR128:$src1,
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(bitconvert (memopv16i8 addr:$src2)), imm:$src3))]>,
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OpSize;
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}
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defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps",
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int_x86_sse41_blendps, 0>;
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defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd",
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int_x86_sse41_blendpd, 0>;
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defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw",
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int_x86_sse41_pblendw, 0>;
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defm DPPS : SS41I_binop_rmi_int<0x40, "dpps",
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int_x86_sse41_dpps, 1>;
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defm DPPD : SS41I_binop_rmi_int<0x41, "dppd",
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int_x86_sse41_dppd, 1>;
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defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw",
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int_x86_sse41_mpsadbw, 0>;
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let Constraints = "$src1 = $dst" in {
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let isCommutable = 0 in {
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defm BLENDPS : SS41I_binop_rmi_int<0x0C, "blendps", int_x86_sse41_blendps>;
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defm BLENDPD : SS41I_binop_rmi_int<0x0D, "blendpd", int_x86_sse41_blendpd>;
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defm PBLENDW : SS41I_binop_rmi_int<0x0E, "pblendw", int_x86_sse41_pblendw>;
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defm MPSADBW : SS41I_binop_rmi_int<0x42, "mpsadbw", int_x86_sse41_mpsadbw>;
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}
|
||||
defm DPPS : SS41I_binop_rmi_int<0x40, "dpps", int_x86_sse41_dpps>;
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||||
defm DPPD : SS41I_binop_rmi_int<0x41, "dppd", int_x86_sse41_dppd>;
|
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}
|
||||
|
||||
/// SS41I_ternary_int - SSE 4.1 ternary operator
|
||||
let Uses = [XMM0], Constraints = "$src1 = $dst" in {
|
||||
|
||||
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Reference in New Issue
Block a user