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Extend r148086 to check for [r +/- reg] address mode. This fixes queens performance regression (due to increased register pressure from overly aggressive pre-inc formation).

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152162 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
2012-03-06 23:33:32 +00:00
parent 4d0983a4d7
commit 03be3622aa
2 changed files with 15 additions and 8 deletions
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11
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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@@ -6142,8 +6142,7 @@ SDValue DAGCombiner::visitBR_CC(SDNode *N) {
/// canFoldInAddressingMode - Return true if 'Use' is a load or a store that
/// uses N as its base pointer and that N may be folded in the load / store
/// addressing mode. FIXME: This currently only looks for folding of
/// [reg +/- imm] addressing modes.
/// addressing mode.
static bool canFoldInAddressingMode(SDNode *N, SDNode *Use,
SelectionDAG &DAG,
const TargetLowering &TLI) {
@@ -6163,15 +6162,19 @@ static bool canFoldInAddressingMode(SDNode *N, SDNode *Use,
if (N->getOpcode() == ISD::ADD) {
ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
if (Offset)
// [reg +/- imm]
AM.BaseOffs = Offset->getSExtValue();
else
return false;
// [reg +/- reg]
AM.Scale = 1;
} else if (N->getOpcode() == ISD::SUB) {
ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
if (Offset)
// [reg +/- imm]
AM.BaseOffs = -Offset->getSExtValue();
else
return false;
// [reg +/- reg]
AM.Scale = 1;
} else
return false;