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Replace string GNU Triples with llvm::Triple in MCAsmBackend subclasses and create*AsmBackend(). NFC.

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Summary:
This continues the patch series to eliminate StringRef forms of GNU triples
from the internals of LLVM that began in r239036.

Reviewers: echristo, rafael

Reviewed By: rafael

Subscribers: rafael, llvm-commits, rengolin

Differential Revision: http://reviews.llvm.org/D10243

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@239464 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Daniel Sanders
2015-06-10 10:35:34 +00:00
parent 189930760d
commit 03c060b6d4
25 changed files with 101 additions and 104 deletions
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14
include/llvm/Support/TargetRegistry.h
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@@ -112,7 +112,7 @@ public:
TargetMachine &TM, std::unique_ptr<MCStreamer> &&Streamer); TargetMachine &TM, std::unique_ptr<MCStreamer> &&Streamer);
typedef MCAsmBackend *(*MCAsmBackendCtorTy)(const Target &T, typedef MCAsmBackend *(*MCAsmBackendCtorTy)(const Target &T,
const MCRegisterInfo &MRI, const MCRegisterInfo &MRI,
StringRef TT, StringRef CPU); const Triple &TT, StringRef CPU);
typedef MCTargetAsmParser *(*MCAsmParserCtorTy)( typedef MCTargetAsmParser *(*MCAsmParserCtorTy)(
MCSubtargetInfo &STI, MCAsmParser &P, const MCInstrInfo &MII, MCSubtargetInfo &STI, MCAsmParser &P, const MCInstrInfo &MII,
const MCTargetOptions &Options); const MCTargetOptions &Options);
@@ -369,12 +369,12 @@ public:
/// createMCAsmBackend - Create a target specific assembly parser. /// createMCAsmBackend - Create a target specific assembly parser.
/// ///
/// \param Triple The target triple string. /// \param TheTriple The target triple string.
MCAsmBackend *createMCAsmBackend(const MCRegisterInfo &MRI, StringRef Triple, MCAsmBackend *createMCAsmBackend(const MCRegisterInfo &MRI,
StringRef CPU) const { StringRef TheTriple, StringRef CPU) const {
if (!MCAsmBackendCtorFn) if (!MCAsmBackendCtorFn)
return nullptr; return nullptr;
return MCAsmBackendCtorFn(*this, MRI, Triple, CPU); return MCAsmBackendCtorFn(*this, MRI, Triple(TheTriple), CPU);
} }
/// createMCAsmParser - Create a target specific assembly parser. /// createMCAsmParser - Create a target specific assembly parser.
@@ -1112,8 +1112,8 @@ template <class MCAsmBackendImpl> struct RegisterMCAsmBackend {
private: private:
static MCAsmBackend *Allocator(const Target &T, const MCRegisterInfo &MRI, static MCAsmBackend *Allocator(const Target &T, const MCRegisterInfo &MRI,
StringRef Triple, StringRef CPU) { const Triple &TheTriple, StringRef CPU) {
return new MCAsmBackendImpl(T, MRI, Triple, CPU); return new MCAsmBackendImpl(T, MRI, TheTriple, CPU);
} }
}; };

14
lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp
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@@ -520,10 +520,9 @@ void ELFAArch64AsmBackend::applyFixup(const MCFixup &Fixup, char *Data,
} }
MCAsmBackend *llvm::createAArch64leAsmBackend(const Target &T, MCAsmBackend *llvm::createAArch64leAsmBackend(const Target &T,
const MCRegisterInfo &MRI, const MCRegisterInfo &MRI,
StringRef TT, StringRef CPU) { const Triple &TheTriple,
Triple TheTriple(TT); StringRef CPU) {
if (TheTriple.isOSDarwin()) if (TheTriple.isOSDarwin())
return new DarwinAArch64AsmBackend(T, MRI); return new DarwinAArch64AsmBackend(T, MRI);
@@ -533,10 +532,9 @@ MCAsmBackend *llvm::createAArch64leAsmBackend(const Target &T,
} }
MCAsmBackend *llvm::createAArch64beAsmBackend(const Target &T, MCAsmBackend *llvm::createAArch64beAsmBackend(const Target &T,
const MCRegisterInfo &MRI, const MCRegisterInfo &MRI,
StringRef TT, StringRef CPU) { const Triple &TheTriple,
Triple TheTriple(TT); StringRef CPU) {
assert(TheTriple.isOSBinFormatELF() && assert(TheTriple.isOSBinFormatELF() &&
"Big endian is only supported for ELF targets!"); "Big endian is only supported for ELF targets!");
uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS()); uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());

8
lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.h
View File

@@ -43,11 +43,11 @@ MCCodeEmitter *createAArch64MCCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI, const MCRegisterInfo &MRI,
MCContext &Ctx); MCContext &Ctx);
MCAsmBackend *createAArch64leAsmBackend(const Target &T, MCAsmBackend *createAArch64leAsmBackend(const Target &T,
const MCRegisterInfo &MRI, StringRef TT, const MCRegisterInfo &MRI,
StringRef CPU); const Triple &TT, StringRef CPU);
MCAsmBackend *createAArch64beAsmBackend(const Target &T, MCAsmBackend *createAArch64beAsmBackend(const Target &T,
const MCRegisterInfo &MRI, StringRef TT, const MCRegisterInfo &MRI,
StringRef CPU); const Triple &TT, StringRef CPU);
MCObjectWriter *createAArch64ELFObjectWriter(raw_pwrite_stream &OS, MCObjectWriter *createAArch64ELFObjectWriter(raw_pwrite_stream &OS,
uint8_t OSABI, uint8_t OSABI,

23
lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
View File

@@ -744,10 +744,9 @@ void ARMAsmBackend::applyFixup(const MCFixup &Fixup, char *Data,
} }
MCAsmBackend *llvm::createARMAsmBackend(const Target &T, MCAsmBackend *llvm::createARMAsmBackend(const Target &T,
const MCRegisterInfo &MRI, StringRef TT, const MCRegisterInfo &MRI,
StringRef CPU, bool isLittle) { const Triple &TheTriple, StringRef CPU,
Triple TheTriple(TT); bool isLittle) {
switch (TheTriple.getObjectFormat()) { switch (TheTriple.getObjectFormat()) {
default: default:
llvm_unreachable("unsupported object format"); llvm_unreachable("unsupported object format");
@@ -764,38 +763,38 @@ MCAsmBackend *llvm::createARMAsmBackend(const Target &T,
.Cases("armv7s", "thumbv7s", MachO::CPU_SUBTYPE_ARM_V7S) .Cases("armv7s", "thumbv7s", MachO::CPU_SUBTYPE_ARM_V7S)
.Default(MachO::CPU_SUBTYPE_ARM_V7); .Default(MachO::CPU_SUBTYPE_ARM_V7);
return new ARMAsmBackendDarwin(T, TT, CS); return new ARMAsmBackendDarwin(T, TheTriple, CS);
} }
case Triple::COFF: case Triple::COFF:
assert(TheTriple.isOSWindows() && "non-Windows ARM COFF is not supported"); assert(TheTriple.isOSWindows() && "non-Windows ARM COFF is not supported");
return new ARMAsmBackendWinCOFF(T, TT); return new ARMAsmBackendWinCOFF(T, TheTriple);
case Triple::ELF: case Triple::ELF:
assert(TheTriple.isOSBinFormatELF() && "using ELF for non-ELF target"); assert(TheTriple.isOSBinFormatELF() && "using ELF for non-ELF target");
uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(Triple(TT).getOS()); uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());
return new ARMAsmBackendELF(T, TT, OSABI, isLittle); return new ARMAsmBackendELF(T, TheTriple, OSABI, isLittle);
} }
} }
MCAsmBackend *llvm::createARMLEAsmBackend(const Target &T, MCAsmBackend *llvm::createARMLEAsmBackend(const Target &T,
const MCRegisterInfo &MRI, const MCRegisterInfo &MRI,
StringRef TT, StringRef CPU) { const Triple &TT, StringRef CPU) {
return createARMAsmBackend(T, MRI, TT, CPU, true); return createARMAsmBackend(T, MRI, TT, CPU, true);
} }
MCAsmBackend *llvm::createARMBEAsmBackend(const Target &T, MCAsmBackend *llvm::createARMBEAsmBackend(const Target &T,
const MCRegisterInfo &MRI, const MCRegisterInfo &MRI,
StringRef TT, StringRef CPU) { const Triple &TT, StringRef CPU) {
return createARMAsmBackend(T, MRI, TT, CPU, false); return createARMAsmBackend(T, MRI, TT, CPU, false);
} }
MCAsmBackend *llvm::createThumbLEAsmBackend(const Target &T, MCAsmBackend *llvm::createThumbLEAsmBackend(const Target &T,
const MCRegisterInfo &MRI, const MCRegisterInfo &MRI,
StringRef TT, StringRef CPU) { const Triple &TT, StringRef CPU) {
return createARMAsmBackend(T, MRI, TT, CPU, true); return createARMAsmBackend(T, MRI, TT, CPU, true);
} }
MCAsmBackend *llvm::createThumbBEAsmBackend(const Target &T, MCAsmBackend *llvm::createThumbBEAsmBackend(const Target &T,
const MCRegisterInfo &MRI, const MCRegisterInfo &MRI,
StringRef TT, StringRef CPU) { const Triple &TT, StringRef CPU) {
return createARMAsmBackend(T, MRI, TT, CPU, false); return createARMAsmBackend(T, MRI, TT, CPU, false);
} }

7
lib/Target/ARM/MCTargetDesc/ARMAsmBackend.h
View File

@@ -23,9 +23,10 @@ class ARMAsmBackend : public MCAsmBackend {
bool isThumbMode; // Currently emitting Thumb code. bool isThumbMode; // Currently emitting Thumb code.
bool IsLittleEndian; // Big or little endian. bool IsLittleEndian; // Big or little endian.
public: public:
ARMAsmBackend(const Target &T, StringRef TT, bool IsLittle) ARMAsmBackend(const Target &T, const Triple &TT, bool IsLittle)
: MCAsmBackend(), STI(ARM_MC::createARMMCSubtargetInfo(TT, "", "")), : MCAsmBackend(), STI(ARM_MC::createARMMCSubtargetInfo(TT.str(), "", "")),
isThumbMode(TT.startswith("thumb")), IsLittleEndian(IsLittle) {} isThumbMode(TT.getArchName().startswith("thumb")),
IsLittleEndian(IsLittle) {}
~ARMAsmBackend() override { delete STI; } ~ARMAsmBackend() override { delete STI; }

3
lib/Target/ARM/MCTargetDesc/ARMAsmBackendDarwin.h
View File

@@ -18,7 +18,8 @@ namespace {
class ARMAsmBackendDarwin : public ARMAsmBackend { class ARMAsmBackendDarwin : public ARMAsmBackend {
public: public:
const MachO::CPUSubTypeARM Subtype; const MachO::CPUSubTypeARM Subtype;
ARMAsmBackendDarwin(const Target &T, StringRef TT, MachO::CPUSubTypeARM st) ARMAsmBackendDarwin(const Target &T, const Triple &TT,
MachO::CPUSubTypeARM st)
: ARMAsmBackend(T, TT, /* IsLittleEndian */ true), Subtype(st) { : ARMAsmBackend(T, TT, /* IsLittleEndian */ true), Subtype(st) {
HasDataInCodeSupport = true; HasDataInCodeSupport = true;
} }

3
lib/Target/ARM/MCTargetDesc/ARMAsmBackendELF.h
View File

@@ -15,7 +15,8 @@ namespace {
class ARMAsmBackendELF : public ARMAsmBackend { class ARMAsmBackendELF : public ARMAsmBackend {
public: public:
uint8_t OSABI; uint8_t OSABI;
ARMAsmBackendELF(const Target &T, StringRef TT, uint8_t OSABI, bool IsLittle) ARMAsmBackendELF(const Target &T, const Triple &TT, uint8_t OSABI,
bool IsLittle)
: ARMAsmBackend(T, TT, IsLittle), OSABI(OSABI) {} : ARMAsmBackend(T, TT, IsLittle), OSABI(OSABI) {}
MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override { MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override {

4
lib/Target/ARM/MCTargetDesc/ARMAsmBackendWinCOFF.h
View File

@@ -15,8 +15,8 @@ using namespace llvm;
namespace { namespace {
class ARMAsmBackendWinCOFF : public ARMAsmBackend { class ARMAsmBackendWinCOFF : public ARMAsmBackend {
public: public:
ARMAsmBackendWinCOFF(const Target &T, StringRef Triple) ARMAsmBackendWinCOFF(const Target &T, const Triple &TheTriple)
: ARMAsmBackend(T, Triple, true) {} : ARMAsmBackend(T, TheTriple, true) {}
MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override { MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override {
return createARMWinCOFFObjectWriter(OS, /*Is64Bit=*/false); return createARMWinCOFFObjectWriter(OS, /*Is64Bit=*/false);
} }

16
lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.h
View File

@@ -65,20 +65,22 @@ MCCodeEmitter *createARMBEMCCodeEmitter(const MCInstrInfo &MCII,
MCContext &Ctx); MCContext &Ctx);
MCAsmBackend *createARMAsmBackend(const Target &T, const MCRegisterInfo &MRI, MCAsmBackend *createARMAsmBackend(const Target &T, const MCRegisterInfo &MRI,
StringRef TT, StringRef CPU, const Triple &TT, StringRef CPU,
bool IsLittleEndian); bool IsLittleEndian);
MCAsmBackend *createARMLEAsmBackend(const Target &T, const MCRegisterInfo &MRI, MCAsmBackend *createARMLEAsmBackend(const Target &T, const MCRegisterInfo &MRI,
StringRef TT, StringRef CPU); const Triple &TT, StringRef CPU);
MCAsmBackend *createARMBEAsmBackend(const Target &T, const MCRegisterInfo &MRI, MCAsmBackend *createARMBEAsmBackend(const Target &T, const MCRegisterInfo &MRI,
StringRef TT, StringRef CPU); const Triple &TT, StringRef CPU);
MCAsmBackend *createThumbLEAsmBackend(const Target &T, const MCRegisterInfo &MRI, MCAsmBackend *createThumbLEAsmBackend(const Target &T,
StringRef TT, StringRef CPU); const MCRegisterInfo &MRI,
const Triple &TT, StringRef CPU);
MCAsmBackend *createThumbBEAsmBackend(const Target &T, const MCRegisterInfo &MRI, MCAsmBackend *createThumbBEAsmBackend(const Target &T,
StringRef TT, StringRef CPU); const MCRegisterInfo &MRI,
const Triple &TT, StringRef CPU);
// Construct a PE/COFF machine code streamer which will generate a PE/COFF // Construct a PE/COFF machine code streamer which will generate a PE/COFF
// object file. // object file.

8
lib/Target/BPF/MCTargetDesc/BPFAsmBackend.cpp
View File

@@ -87,13 +87,13 @@ MCObjectWriter *BPFAsmBackend::createObjectWriter(raw_pwrite_stream &OS) const {
} }
MCAsmBackend *llvm::createBPFAsmBackend(const Target &T, MCAsmBackend *llvm::createBPFAsmBackend(const Target &T,
const MCRegisterInfo &MRI, StringRef TT, const MCRegisterInfo &MRI,
StringRef CPU) { const Triple &TT, StringRef CPU) {
return new BPFAsmBackend(/*IsLittleEndian=*/true); return new BPFAsmBackend(/*IsLittleEndian=*/true);
} }
MCAsmBackend *llvm::createBPFbeAsmBackend(const Target &T, MCAsmBackend *llvm::createBPFbeAsmBackend(const Target &T,
const MCRegisterInfo &MRI, StringRef TT, const MCRegisterInfo &MRI,
StringRef CPU) { const Triple &TT, StringRef CPU) {
return new BPFAsmBackend(/*IsLittleEndian=*/false); return new BPFAsmBackend(/*IsLittleEndian=*/false);
} }

7
lib/Target/BPF/MCTargetDesc/BPFMCTargetDesc.h
View File

@@ -25,8 +25,9 @@ class MCInstrInfo;
class MCObjectWriter; class MCObjectWriter;
class MCRegisterInfo; class MCRegisterInfo;
class MCSubtargetInfo; class MCSubtargetInfo;
class Target;
class StringRef; class StringRef;
class Target;
class Triple;
class raw_ostream; class raw_ostream;
class raw_pwrite_stream; class raw_pwrite_stream;
@@ -42,9 +43,9 @@ MCCodeEmitter *createBPFbeMCCodeEmitter(const MCInstrInfo &MCII,
MCContext &Ctx); MCContext &Ctx);
MCAsmBackend *createBPFAsmBackend(const Target &T, const MCRegisterInfo &MRI, MCAsmBackend *createBPFAsmBackend(const Target &T, const MCRegisterInfo &MRI,
StringRef TT, StringRef CPU); const Triple &TT, StringRef CPU);
MCAsmBackend *createBPFbeAsmBackend(const Target &T, const MCRegisterInfo &MRI, MCAsmBackend *createBPFbeAsmBackend(const Target &T, const MCRegisterInfo &MRI,
StringRef TT, StringRef CPU); const Triple &TT, StringRef CPU);
MCObjectWriter *createBPFELFObjectWriter(raw_pwrite_stream &OS, MCObjectWriter *createBPFELFObjectWriter(raw_pwrite_stream &OS,
uint8_t OSABI, bool IsLittleEndian); uint8_t OSABI, bool IsLittleEndian);

4
lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp
View File

@@ -288,8 +288,8 @@ public:
namespace llvm { namespace llvm {
MCAsmBackend *createHexagonAsmBackend(Target const &T, MCAsmBackend *createHexagonAsmBackend(Target const &T,
MCRegisterInfo const & /*MRI*/, MCRegisterInfo const & /*MRI*/,
StringRef TT, StringRef CPU) { const Triple &TT, StringRef CPU) {
uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(Triple(TT).getOS()); uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS());
return new HexagonAsmBackend(T, OSABI, CPU); return new HexagonAsmBackend(T, OSABI, CPU);
} }
} }

5
lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h
View File

@@ -27,6 +27,7 @@ class MCObjectWriter;
class MCRegisterInfo; class MCRegisterInfo;
class MCSubtargetInfo; class MCSubtargetInfo;
class Target; class Target;
class Triple;
class StringRef; class StringRef;
class raw_ostream; class raw_ostream;
class raw_pwrite_stream; class raw_pwrite_stream;
@@ -42,8 +43,8 @@ MCCodeEmitter *createHexagonMCCodeEmitter(MCInstrInfo const &MCII,
MCContext &MCT); MCContext &MCT);
MCAsmBackend *createHexagonAsmBackend(Target const &T, MCAsmBackend *createHexagonAsmBackend(Target const &T,
MCRegisterInfo const &MRI, StringRef TT, MCRegisterInfo const &MRI,
StringRef CPU); const Triple &TT, StringRef CPU);
MCObjectWriter *createHexagonELFObjectWriter(raw_pwrite_stream &OS, MCObjectWriter *createHexagonELFObjectWriter(raw_pwrite_stream &OS,
uint8_t OSABI, StringRef CPU); uint8_t OSABI, StringRef CPU);

27
lib/Target/Mips/MCTargetDesc/MipsAsmBackend.cpp
View File

@@ -417,32 +417,27 @@ void MipsAsmBackend::processFixupValue(const MCAssembler &Asm,
// MCAsmBackend // MCAsmBackend
MCAsmBackend *llvm::createMipsAsmBackendEL32(const Target &T, MCAsmBackend *llvm::createMipsAsmBackendEL32(const Target &T,
const MCRegisterInfo &MRI, const MCRegisterInfo &MRI,
StringRef TT, const Triple &TT, StringRef CPU) {
StringRef CPU) { return new MipsAsmBackend(T, TT.getOS(), /*IsLittle*/ true,
return new MipsAsmBackend(T, Triple(TT).getOS(), /*Is64Bit*/ false);
/*IsLittle*/true, /*Is64Bit*/false);
} }
MCAsmBackend *llvm::createMipsAsmBackendEB32(const Target &T, MCAsmBackend *llvm::createMipsAsmBackendEB32(const Target &T,
const MCRegisterInfo &MRI, const MCRegisterInfo &MRI,
StringRef TT, const Triple &TT, StringRef CPU) {
StringRef CPU) { return new MipsAsmBackend(T, TT.getOS(), /*IsLittle*/ false,
return new MipsAsmBackend(T, Triple(TT).getOS(), /*Is64Bit*/ false);
/*IsLittle*/false, /*Is64Bit*/false);
} }
MCAsmBackend *llvm::createMipsAsmBackendEL64(const Target &T, MCAsmBackend *llvm::createMipsAsmBackendEL64(const Target &T,
const MCRegisterInfo &MRI, const MCRegisterInfo &MRI,
StringRef TT, const Triple &TT, StringRef CPU) {
StringRef CPU) { return new MipsAsmBackend(T, TT.getOS(), /*IsLittle*/ true, /*Is64Bit*/ true);
return new MipsAsmBackend(T, Triple(TT).getOS(),
/*IsLittle*/true, /*Is64Bit*/true);
} }
MCAsmBackend *llvm::createMipsAsmBackendEB64(const Target &T, MCAsmBackend *llvm::createMipsAsmBackendEB64(const Target &T,
const MCRegisterInfo &MRI, const MCRegisterInfo &MRI,
StringRef TT, const Triple &TT, StringRef CPU) {
StringRef CPU) { return new MipsAsmBackend(T, TT.getOS(), /*IsLittle*/ false,
return new MipsAsmBackend(T, Triple(TT).getOS(), /*Is64Bit*/ true);
/*IsLittle*/false, /*Is64Bit*/true);
} }

17
lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h
View File

@@ -26,6 +26,7 @@ class MCRegisterInfo;
class MCSubtargetInfo; class MCSubtargetInfo;
class StringRef; class StringRef;
class Target; class Target;
class Triple;
class raw_ostream; class raw_ostream;
class raw_pwrite_stream; class raw_pwrite_stream;
@@ -42,17 +43,17 @@ MCCodeEmitter *createMipsMCCodeEmitterEL(const MCInstrInfo &MCII,
MCContext &Ctx); MCContext &Ctx);
MCAsmBackend *createMipsAsmBackendEB32(const Target &T, MCAsmBackend *createMipsAsmBackendEB32(const Target &T,
const MCRegisterInfo &MRI, StringRef TT, const MCRegisterInfo &MRI,
StringRef CPU); const Triple &TT, StringRef CPU);
MCAsmBackend *createMipsAsmBackendEL32(const Target &T, MCAsmBackend *createMipsAsmBackendEL32(const Target &T,
const MCRegisterInfo &MRI, StringRef TT, const MCRegisterInfo &MRI,
StringRef CPU); const Triple &TT, StringRef CPU);
MCAsmBackend *createMipsAsmBackendEB64(const Target &T, MCAsmBackend *createMipsAsmBackendEB64(const Target &T,
const MCRegisterInfo &MRI, StringRef TT, const MCRegisterInfo &MRI,
StringRef CPU); const Triple &TT, StringRef CPU);
MCAsmBackend *createMipsAsmBackendEL64(const Target &T, MCAsmBackend *createMipsAsmBackendEL64(const Target &T,
const MCRegisterInfo &MRI, StringRef TT, const MCRegisterInfo &MRI,
StringRef CPU); const Triple &TT, StringRef CPU);
MCObjectWriter *createMipsELFObjectWriter(raw_pwrite_stream &OS, uint8_t OSABI, MCObjectWriter *createMipsELFObjectWriter(raw_pwrite_stream &OS, uint8_t OSABI,
bool IsLittleEndian, bool Is64Bit); bool IsLittleEndian, bool Is64Bit);

8
lib/Target/PowerPC/MCTargetDesc/PPCAsmBackend.cpp
View File

@@ -230,11 +230,11 @@ namespace {
MCAsmBackend *llvm::createPPCAsmBackend(const Target &T, MCAsmBackend *llvm::createPPCAsmBackend(const Target &T,
const MCRegisterInfo &MRI, const MCRegisterInfo &MRI,
StringRef TT, StringRef CPU) { const Triple &TT, StringRef CPU) {
if (Triple(TT).isOSDarwin()) if (TT.isOSDarwin())
return new DarwinPPCAsmBackend(T); return new DarwinPPCAsmBackend(T);
uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(Triple(TT).getOS()); uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS());
bool IsLittleEndian = Triple(TT).getArch() == Triple::ppc64le; bool IsLittleEndian = TT.getArch() == Triple::ppc64le;
return new ELFPPCAsmBackend(T, IsLittleEndian, OSABI); return new ELFPPCAsmBackend(T, IsLittleEndian, OSABI);
} }

3
lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h
View File

@@ -29,6 +29,7 @@ class MCObjectWriter;
class MCRegisterInfo; class MCRegisterInfo;
class MCSubtargetInfo; class MCSubtargetInfo;
class Target; class Target;
class Triple;
class StringRef; class StringRef;
class raw_pwrite_stream; class raw_pwrite_stream;
class raw_ostream; class raw_ostream;
@@ -42,7 +43,7 @@ MCCodeEmitter *createPPCMCCodeEmitter(const MCInstrInfo &MCII,
MCContext &Ctx); MCContext &Ctx);
MCAsmBackend *createPPCAsmBackend(const Target &T, const MCRegisterInfo &MRI, MCAsmBackend *createPPCAsmBackend(const Target &T, const MCRegisterInfo &MRI,
StringRef TT, StringRef CPU); const Triple &TT, StringRef CPU);
/// Construct an PPC ELF object writer. /// Construct an PPC ELF object writer.
MCObjectWriter *createPPCELFObjectWriter(raw_pwrite_stream &OS, bool Is64Bit, MCObjectWriter *createPPCELFObjectWriter(raw_pwrite_stream &OS, bool Is64Bit,

3
lib/Target/R600/MCTargetDesc/AMDGPUAsmBackend.cpp
View File

@@ -139,7 +139,6 @@ public:
MCAsmBackend *llvm::createAMDGPUAsmBackend(const Target &T, MCAsmBackend *llvm::createAMDGPUAsmBackend(const Target &T,
const MCRegisterInfo &MRI, const MCRegisterInfo &MRI,
StringRef TT, const Triple &TT, StringRef CPU) {
StringRef CPU) {
return new ELFAMDGPUAsmBackend(T); return new ELFAMDGPUAsmBackend(T);
} }

3
lib/Target/R600/MCTargetDesc/AMDGPUMCTargetDesc.h
View File

@@ -28,6 +28,7 @@ class MCObjectWriter;
class MCRegisterInfo; class MCRegisterInfo;
class MCSubtargetInfo; class MCSubtargetInfo;
class Target; class Target;
class Triple;
class raw_pwrite_stream; class raw_pwrite_stream;
class raw_ostream; class raw_ostream;
@@ -43,7 +44,7 @@ MCCodeEmitter *createSIMCCodeEmitter(const MCInstrInfo &MCII,
MCContext &Ctx); MCContext &Ctx);
MCAsmBackend *createAMDGPUAsmBackend(const Target &T, const MCRegisterInfo &MRI, MCAsmBackend *createAMDGPUAsmBackend(const Target &T, const MCRegisterInfo &MRI,
StringRef TT, StringRef CPU); const Triple &TT, StringRef CPU);
MCObjectWriter *createAMDGPUELFObjectWriter(raw_pwrite_stream &OS); MCObjectWriter *createAMDGPUELFObjectWriter(raw_pwrite_stream &OS);
} // End llvm namespace } // End llvm namespace

6
lib/Target/Sparc/MCTargetDesc/SparcAsmBackend.cpp
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@@ -297,10 +297,8 @@ namespace {
} // end anonymous namespace } // end anonymous namespace
MCAsmBackend *llvm::createSparcAsmBackend(const Target &T, MCAsmBackend *llvm::createSparcAsmBackend(const Target &T,
const MCRegisterInfo &MRI, const MCRegisterInfo &MRI,
StringRef TT, const Triple &TT, StringRef CPU) {
StringRef CPU) { return new ELFSparcAsmBackend(T, TT.getOS());
return new ELFSparcAsmBackend(T, Triple(TT).getOS());
} }

3
lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.h
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@@ -25,6 +25,7 @@ class MCObjectWriter;
class MCRegisterInfo; class MCRegisterInfo;
class MCSubtargetInfo; class MCSubtargetInfo;
class Target; class Target;
class Triple;
class StringRef; class StringRef;
class raw_pwrite_stream; class raw_pwrite_stream;
class raw_ostream; class raw_ostream;
@@ -37,7 +38,7 @@ MCCodeEmitter *createSparcMCCodeEmitter(const MCInstrInfo &MCII,
const MCRegisterInfo &MRI, const MCRegisterInfo &MRI,
MCContext &Ctx); MCContext &Ctx);
MCAsmBackend *createSparcAsmBackend(const Target &T, const MCRegisterInfo &MRI, MCAsmBackend *createSparcAsmBackend(const Target &T, const MCRegisterInfo &MRI,
StringRef TT, StringRef CPU); const Triple &TT, StringRef CPU);
MCObjectWriter *createSparcELFObjectWriter(raw_pwrite_stream &OS, bool Is64Bit, MCObjectWriter *createSparcELFObjectWriter(raw_pwrite_stream &OS, bool Is64Bit,
bool IsLIttleEndian, uint8_t OSABI); bool IsLIttleEndian, uint8_t OSABI);
} // End llvm namespace } // End llvm namespace

4
lib/Target/SystemZ/MCTargetDesc/SystemZMCAsmBackend.cpp
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@@ -111,7 +111,7 @@ bool SystemZMCAsmBackend::writeNopData(uint64_t Count,
MCAsmBackend *llvm::createSystemZMCAsmBackend(const Target &T, MCAsmBackend *llvm::createSystemZMCAsmBackend(const Target &T,
const MCRegisterInfo &MRI, const MCRegisterInfo &MRI,
StringRef TT, StringRef CPU) { const Triple &TT, StringRef CPU) {
uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(Triple(TT).getOS()); uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS());
return new SystemZMCAsmBackend(OSABI); return new SystemZMCAsmBackend(OSABI);
} }

3
lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.h
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@@ -23,6 +23,7 @@ class MCRegisterInfo;
class MCSubtargetInfo; class MCSubtargetInfo;
class StringRef; class StringRef;
class Target; class Target;
class Triple;
class raw_pwrite_stream; class raw_pwrite_stream;
class raw_ostream; class raw_ostream;
@@ -84,7 +85,7 @@ MCCodeEmitter *createSystemZMCCodeEmitter(const MCInstrInfo &MCII,
MCAsmBackend *createSystemZMCAsmBackend(const Target &T, MCAsmBackend *createSystemZMCAsmBackend(const Target &T,
const MCRegisterInfo &MRI, const MCRegisterInfo &MRI,
StringRef TT, StringRef CPU); const Triple &TT, StringRef CPU);
MCObjectWriter *createSystemZObjectWriter(raw_pwrite_stream &OS, uint8_t OSABI); MCObjectWriter *createSystemZObjectWriter(raw_pwrite_stream &OS, uint8_t OSABI);
} // end namespace llvm } // end namespace llvm

8
lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
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@@ -790,10 +790,8 @@ public:
MCAsmBackend *llvm::createX86_32AsmBackend(const Target &T, MCAsmBackend *llvm::createX86_32AsmBackend(const Target &T,
const MCRegisterInfo &MRI, const MCRegisterInfo &MRI,
StringRef TT, const Triple &TheTriple,
StringRef CPU) { StringRef CPU) {
Triple TheTriple(TT);
if (TheTriple.isOSBinFormatMachO()) if (TheTriple.isOSBinFormatMachO())
return new DarwinX86_32AsmBackend(T, MRI, CPU); return new DarwinX86_32AsmBackend(T, MRI, CPU);
@@ -806,10 +804,8 @@ MCAsmBackend *llvm::createX86_32AsmBackend(const Target &T,
MCAsmBackend *llvm::createX86_64AsmBackend(const Target &T, MCAsmBackend *llvm::createX86_64AsmBackend(const Target &T,
const MCRegisterInfo &MRI, const MCRegisterInfo &MRI,
StringRef TT, const Triple &TheTriple,
StringRef CPU) { StringRef CPU) {
Triple TheTriple(TT);
if (TheTriple.isOSBinFormatMachO()) { if (TheTriple.isOSBinFormatMachO()) {
MachO::CPUSubTypeX86 CS = MachO::CPUSubTypeX86 CS =
StringSwitch<MachO::CPUSubTypeX86>(TheTriple.getArchName()) StringSwitch<MachO::CPUSubTypeX86>(TheTriple.getArchName())

4
lib/Target/X86/MCTargetDesc/X86MCTargetDesc.h
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@@ -69,9 +69,9 @@ MCCodeEmitter *createX86MCCodeEmitter(const MCInstrInfo &MCII,
MCContext &Ctx); MCContext &Ctx);
MCAsmBackend *createX86_32AsmBackend(const Target &T, const MCRegisterInfo &MRI, MCAsmBackend *createX86_32AsmBackend(const Target &T, const MCRegisterInfo &MRI,
StringRef TT, StringRef CPU); const Triple &TT, StringRef CPU);
MCAsmBackend *createX86_64AsmBackend(const Target &T, const MCRegisterInfo &MRI, MCAsmBackend *createX86_64AsmBackend(const Target &T, const MCRegisterInfo &MRI,
StringRef TT, StringRef CPU); const Triple &TT, StringRef CPU);
/// Construct an X86 Windows COFF machine code streamer which will generate /// Construct an X86 Windows COFF machine code streamer which will generate
/// PE/COFF format object files. /// PE/COFF format object files.