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[NVPTX] Handle signext/zeroext attributes properly

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Fix a case where we were incorrectly sign-extending a value when we should have been zero-extending the value.

Also change some SIGN_EXTEND to ANY_EXTEND because we really dont care and may have more opportunity to fold subexpressions

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185331 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Justin Holewinski
2013-07-01 12:58:58 +00:00
parent 8834184a46
commit 03e5bb2c87
2 changed files with 41 additions and 19 deletions
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38
lib/Target/NVPTX/NVPTXISelLowering.cpp
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@@ -713,7 +713,7 @@ SDValue NVPTXTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
sz = 8; sz = 8;
SDValue StVal = OutVals[OIdx]; SDValue StVal = OutVals[OIdx];
if (elemtype.getSizeInBits() < 16) { if (elemtype.getSizeInBits() < 16) {
StVal = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i16, StVal); StVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i16, StVal);
} }
SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue); SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
SDValue CopyParamOps[] = { Chain, SDValue CopyParamOps[] = { Chain,
@@ -947,7 +947,7 @@ SDValue NVPTXTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
MachinePointerInfo(), false, false, false, MachinePointerInfo(), false, false, false,
0); 0);
if (elemtype.getSizeInBits() < 16) { if (elemtype.getSizeInBits() < 16) {
theVal = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i16, theVal); theVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i16, theVal);
} }
SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue); SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
SDValue CopyParamOps[] = { Chain, DAG.getConstant(paramCount, MVT::i32), SDValue CopyParamOps[] = { Chain, DAG.getConstant(paramCount, MVT::i32),
@@ -1382,9 +1382,9 @@ NVPTXTargetLowering::LowerSTOREVector(SDValue Op, SelectionDAG &DAG) const {
// Since StoreV2 is a target node, we cannot rely on DAG type legalization. // Since StoreV2 is a target node, we cannot rely on DAG type legalization.
// Therefore, we must ensure the type is legal. For i1 and i8, we set the // Therefore, we must ensure the type is legal. For i1 and i8, we set the
// stored type to i16 and propogate the "real" type as the memory type. // stored type to i16 and propogate the "real" type as the memory type.
bool NeedSExt = false; bool NeedExt = false;
if (EltVT.getSizeInBits() < 16) if (EltVT.getSizeInBits() < 16)
NeedSExt = true; NeedExt = true;
switch (NumElts) { switch (NumElts) {
default: default:
@@ -1407,8 +1407,8 @@ NVPTXTargetLowering::LowerSTOREVector(SDValue Op, SelectionDAG &DAG) const {
for (unsigned i = 0; i < NumElts; ++i) { for (unsigned i = 0; i < NumElts; ++i) {
SDValue ExtVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, Val, SDValue ExtVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, Val,
DAG.getIntPtrConstant(i)); DAG.getIntPtrConstant(i));
if (NeedSExt) if (NeedExt)
ExtVal = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i16, ExtVal); ExtVal = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i16, ExtVal);
Ops.push_back(ExtVal); Ops.push_back(ExtVal);
} }
@@ -1615,14 +1615,17 @@ SDValue NVPTXTargetLowering::LowerFormalArguments(
: TD->getABITypeAlignment( : TD->getABITypeAlignment(
partVT.getTypeForEVT(F->getContext())); partVT.getTypeForEVT(F->getContext()));
SDValue p; SDValue p;
if (Ins[InsIdx].VT.getSizeInBits() > partVT.getSizeInBits()) if (Ins[InsIdx].VT.getSizeInBits() > partVT.getSizeInBits()) {
p = DAG.getExtLoad(ISD::SEXTLOAD, dl, Ins[InsIdx].VT, Root, srcAddr, ISD::LoadExtType ExtOp = Ins[InsIdx].Flags.isSExt() ?
ISD::SEXTLOAD : ISD::ZEXTLOAD;
p = DAG.getExtLoad(ExtOp, dl, Ins[InsIdx].VT, Root, srcAddr,
MachinePointerInfo(srcValue), partVT, false, MachinePointerInfo(srcValue), partVT, false,
false, partAlign); false, partAlign);
else } else {
p = DAG.getLoad(partVT, dl, Root, srcAddr, p = DAG.getLoad(partVT, dl, Root, srcAddr,
MachinePointerInfo(srcValue), false, false, false, MachinePointerInfo(srcValue), false, false, false,
partAlign); partAlign);
}
if (p.getNode()) if (p.getNode())
p.getNode()->setIROrder(idx + 1); p.getNode()->setIROrder(idx + 1);
InVals.push_back(p); InVals.push_back(p);
@@ -1657,7 +1660,7 @@ SDValue NVPTXTargetLowering::LowerFormalArguments(
P.getNode()->setIROrder(idx + 1); P.getNode()->setIROrder(idx + 1);
if (Ins[InsIdx].VT.getSizeInBits() > EltVT.getSizeInBits()) if (Ins[InsIdx].VT.getSizeInBits() > EltVT.getSizeInBits())
P = DAG.getNode(ISD::SIGN_EXTEND, dl, Ins[InsIdx].VT, P); P = DAG.getNode(ISD::ANY_EXTEND, dl, Ins[InsIdx].VT, P);
InVals.push_back(P); InVals.push_back(P);
Ofst += TD->getTypeAllocSize(EltVT.getTypeForEVT(F->getContext())); Ofst += TD->getTypeAllocSize(EltVT.getTypeForEVT(F->getContext()));
++InsIdx; ++InsIdx;
@@ -1682,8 +1685,8 @@ SDValue NVPTXTargetLowering::LowerFormalArguments(
DAG.getIntPtrConstant(1)); DAG.getIntPtrConstant(1));
if (Ins[InsIdx].VT.getSizeInBits() > EltVT.getSizeInBits()) { if (Ins[InsIdx].VT.getSizeInBits() > EltVT.getSizeInBits()) {
Elt0 = DAG.getNode(ISD::SIGN_EXTEND, dl, Ins[InsIdx].VT, Elt0); Elt0 = DAG.getNode(ISD::ANY_EXTEND, dl, Ins[InsIdx].VT, Elt0);
Elt1 = DAG.getNode(ISD::SIGN_EXTEND, dl, Ins[InsIdx].VT, Elt1); Elt1 = DAG.getNode(ISD::ANY_EXTEND, dl, Ins[InsIdx].VT, Elt1);
} }
InVals.push_back(Elt0); InVals.push_back(Elt0);
@@ -1726,7 +1729,7 @@ SDValue NVPTXTargetLowering::LowerFormalArguments(
SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, P, SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, P,
DAG.getIntPtrConstant(j)); DAG.getIntPtrConstant(j));
if (Ins[InsIdx].VT.getSizeInBits() > EltVT.getSizeInBits()) if (Ins[InsIdx].VT.getSizeInBits() > EltVT.getSizeInBits())
Elt = DAG.getNode(ISD::SIGN_EXTEND, dl, Ins[InsIdx].VT, Elt); Elt = DAG.getNode(ISD::ANY_EXTEND, dl, Ins[InsIdx].VT, Elt);
InVals.push_back(Elt); InVals.push_back(Elt);
} }
Ofst += TD->getTypeAllocSize(VecVT.getTypeForEVT(F->getContext())); Ofst += TD->getTypeAllocSize(VecVT.getTypeForEVT(F->getContext()));
@@ -1745,14 +1748,17 @@ SDValue NVPTXTargetLowering::LowerFormalArguments(
Value *srcValue = Constant::getNullValue(PointerType::get( Value *srcValue = Constant::getNullValue(PointerType::get(
ObjectVT.getTypeForEVT(F->getContext()), llvm::ADDRESS_SPACE_PARAM)); ObjectVT.getTypeForEVT(F->getContext()), llvm::ADDRESS_SPACE_PARAM));
SDValue p; SDValue p;
if (ObjectVT.getSizeInBits() < Ins[InsIdx].VT.getSizeInBits()) if (ObjectVT.getSizeInBits() < Ins[InsIdx].VT.getSizeInBits()) {
p = DAG.getExtLoad(ISD::SEXTLOAD, dl, Ins[InsIdx].VT, Root, Arg, ISD::LoadExtType ExtOp = Ins[InsIdx].Flags.isSExt() ?
ISD::SEXTLOAD : ISD::ZEXTLOAD;
p = DAG.getExtLoad(ExtOp, dl, Ins[InsIdx].VT, Root, Arg,
MachinePointerInfo(srcValue), ObjectVT, false, false, MachinePointerInfo(srcValue), ObjectVT, false, false,
TD->getABITypeAlignment(ObjectVT.getTypeForEVT(F->getContext()))); TD->getABITypeAlignment(ObjectVT.getTypeForEVT(F->getContext())));
else } else {
p = DAG.getLoad(Ins[InsIdx].VT, dl, Root, Arg, p = DAG.getLoad(Ins[InsIdx].VT, dl, Root, Arg,
MachinePointerInfo(srcValue), false, false, false, MachinePointerInfo(srcValue), false, false, false,
TD->getABITypeAlignment(ObjectVT.getTypeForEVT(F->getContext()))); TD->getABITypeAlignment(ObjectVT.getTypeForEVT(F->getContext())));
}
if (p.getNode()) if (p.getNode())
p.getNode()->setIROrder(idx + 1); p.getNode()->setIROrder(idx + 1);
InVals.push_back(p); InVals.push_back(p);

16
test/CodeGen/NVPTX/sext-params.ll Normal file
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@@ -0,0 +1,16 @@
; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64"
define i8 @foo(i8 signext %a) {
; CHECK: ld.param.s8
%ret = add i8 %a, 3
ret i8 %ret
}
define i8 @bar(i8 zeroext %a) {
; CHECK: ld.param.u8
%ret = add i8 %a, 3
ret i8 %ret
}