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Fix PR1763 by allowing the 'q' constraint to work with 64-bit

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regs on x86-64.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43669 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2007-11-04 06:51:12 +00:00
parent 0647ebf1dc
commit 03e6c7091e
2 changed files with 12 additions and 1 deletions
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4
lib/Target/X86/X86ISelLowering.cpp
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@ -5708,7 +5708,9 @@ getRegClassForInlineAsmConstraint(const std::string &Constraint,
return make_vector<unsigned>(X86::AX, X86::DX, X86::CX, X86::BX, 0);
else if (VT == MVT::i8)
return make_vector<unsigned>(X86::AL, X86::DL, X86::CL, X86::BL, 0);
break;
else if (VT == MVT::i64)
return make_vector<unsigned>(X86::RAX, X86::RDX, X86::RCX, X86::RBX, 0);
break;
}
}

9
test/CodeGen/X86/2007-11-03-x86-64-q-constraint.ll Normal file
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@ -0,0 +1,9 @@
; RUN: llvm-as < %s | llc
; PR1763
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
target triple = "x86_64-unknown-linux-gnu"
define void @yield() {
%tmp9 = call i64 asm sideeffect "xchgb ${0:b},$1", "=q,*m,0,~{dirflag},~{fpsr},~{flags},~{memory}"( i64* null, i64 0 ) ; <i64>
ret void
}