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Fixed a bug in disassembly of STR_POST, where the immediate is the second operand in am2offset;

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instead of the second operand in addrmode_imm12.

rdar://problem/9225289


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128757 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Johnny Chen 2011-04-02 02:24:54 +00:00
parent ad8ffad60a
commit 04187ecd57
2 changed files with 16 additions and 5 deletions
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18
lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
View File

@ -1098,12 +1098,20 @@ static bool DisassembleLdStFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
OpIdx += 1;
}
// Disassemble the 12-bit immediate offset, which is the second operand in
// $addrmode_imm12 => (ops GPR:$base, i32imm:$offsimm).
//
unsigned Imm12 = slice(insn, 11, 0);
int Offset = AddrOpcode == ARM_AM::add ? 1 * Imm12 : -1 * Imm12;
MI.addOperand(MCOperand::CreateImm(Offset));
if (Opcode == ARM::LDRBi12 || Opcode == ARM::LDRi12 ||
Opcode == ARM::STRBi12 || Opcode == ARM::STRi12) {
// Disassemble the 12-bit immediate offset, which is the second operand in
// $addrmode_imm12 => (ops GPR:$base, i32imm:$offsimm).
int Offset = AddrOpcode == ARM_AM::add ? 1 * Imm12 : -1 * Imm12;
MI.addOperand(MCOperand::CreateImm(Offset));
} else {
// Disassemble the 12-bit immediate offset, which is the second operand in
// $am2offset => (ops GPR, i32imm).
unsigned Offset = ARM_AM::getAM2Opc(AddrOpcode, Imm12, ARM_AM::no_shift,
IndexMode);
MI.addOperand(MCOperand::CreateImm(Offset));
}
OpIdx += 1;
} else {
// The opcode ARM::LDRT actually corresponds to both Encoding A1 and A2 of

3
test/MC/Disassembler/ARM/arm-tests.txt
View File

@ -233,3 +233,6 @@
# CHECK: adcshi r10, r8, r0, asr r3
0x50 0xa3 0xb8 0x80
# CHECK: streq r1, [sp], #-1567
0x1f 0x16 0xd 0x4