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Refactoring of more SSE conversion instructions. Also add some AVX instrinsics Int_V... placeholders
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106867 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bruno Cardoso Lopes
parent
493315922b
commit
0491e132fc
@ -444,46 +444,6 @@ multiclass sse12_fp_packed_int<bits<8> opc, string OpcodeStr, RegisterClass RC,
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RC:$src1, (mem_frag addr:$src2)))], d>;
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}
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//===----------------------------------------------------------------------===//
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// SSE1 Instructions
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//===----------------------------------------------------------------------===//
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// Conversion Instructions
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// Match intrinsics which expect XMM operand(s).
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def CVTSS2SIrr: SSI<0x2D, MRMSrcReg, (outs GR32:$dst), (ins FR32:$src),
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"cvtss2si{l}\t{$src, $dst|$dst, $src}", []>;
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def CVTSS2SIrm: SSI<0x2D, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
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"cvtss2si{l}\t{$src, $dst|$dst, $src}", []>;
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def CVTDQ2PSrr : PSI<0x5B, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src),
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"cvtdq2ps\t{$src, $dst|$dst, $src}", []>;
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def CVTDQ2PSrm : PSI<0x5B, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
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"cvtdq2ps\t{$src, $dst|$dst, $src}", []>;
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// Aliases for intrinsics
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def Int_CVTTSS2SIrr : SSI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
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"cvttss2si\t{$src, $dst|$dst, $src}",
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[(set GR32:$dst,
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(int_x86_sse_cvttss2si VR128:$src))]>;
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def Int_CVTTSS2SIrm : SSI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f32mem:$src),
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"cvttss2si\t{$src, $dst|$dst, $src}",
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[(set GR32:$dst,
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(int_x86_sse_cvttss2si(load addr:$src)))]>;
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let Constraints = "$src1 = $dst" in {
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def Int_CVTSI2SSrr : SSI<0x2A, MRMSrcReg,
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(outs VR128:$dst), (ins VR128:$src1, GR32:$src2),
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"cvtsi2ss\t{$src2, $dst|$dst, $src2}",
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[(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
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GR32:$src2))]>;
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def Int_CVTSI2SSrm : SSI<0x2A, MRMSrcMem,
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(outs VR128:$dst), (ins VR128:$src1, i32mem:$src2),
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"cvtsi2ss\t{$src2, $dst|$dst, $src2}",
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[(set VR128:$dst, (int_x86_sse_cvtsi2ss VR128:$src1,
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(loadi32 addr:$src2)))]>;
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}
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//===----------------------------------------------------------------------===//
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// SSE 1 & 2 - Move Instructions
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//===----------------------------------------------------------------------===//
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@ -604,7 +564,7 @@ def : Pat<(store (f64 (vector_extract (v2f64 VR128:$src), (iPTR 0))),
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// SSE 1 & 2 - Conversion Instructions
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//===----------------------------------------------------------------------===//
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multiclass sse12_cvt<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
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multiclass sse12_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
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SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
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string asm> {
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def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
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@ -613,7 +573,16 @@ multiclass sse12_cvt<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
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[(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>;
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}
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multiclass sse12_cvt_avx<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
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multiclass sse12_cvt_p<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
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SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
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string asm, Domain d> {
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def rr : PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
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[(set DstRC:$dst, (OpNode SrcRC:$src))], d>;
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def rm : PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
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[(set DstRC:$dst, (OpNode (ld_frag addr:$src)))], d>;
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}
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multiclass sse12_vcvt_avx<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
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SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
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string asm> {
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def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
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@ -622,47 +591,30 @@ multiclass sse12_cvt_avx<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
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(ins DstRC:$src1, x86memop:$src), asm, []>;
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}
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// Conversion instructions
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let isAsmParserOnly = 1 in {
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defm VCVTTSS2SI : sse12_cvt<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
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defm VCVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
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"cvttss2si\t{$src, $dst|$dst, $src}">, XS, VEX;
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defm VCVTTSD2SI : sse12_cvt<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
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defm VCVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
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"cvttsd2si\t{$src, $dst|$dst, $src}">, XD, VEX;
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}
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defm CVTTSS2SI : sse12_cvt<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
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"cvttss2si\t{$src, $dst|$dst, $src}">, XS;
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defm CVTTSD2SI : sse12_cvt<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
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"cvttsd2si\t{$src, $dst|$dst, $src}">, XD;
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let isAsmParserOnly = 1 in {
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defm VCVTSI2SS : sse12_cvt_avx<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32,
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defm VCVTSI2SS : sse12_vcvt_avx<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32,
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"cvtsi2ss\t{$src, $src1, $dst|$dst, $src1, $src}">, XS,
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VEX_4V;
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defm VCVTSI2SD : sse12_cvt_avx<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32,
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defm VCVTSI2SD : sse12_vcvt_avx<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32,
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"cvtsi2sd\t{$src, $src1, $dst|$dst, $src1, $src}">, XD,
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VEX_4V;
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}
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defm CVTSI2SS : sse12_cvt<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32,
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defm CVTTSS2SI : sse12_cvt_s<0x2C, FR32, GR32, fp_to_sint, f32mem, loadf32,
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"cvttss2si\t{$src, $dst|$dst, $src}">, XS;
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defm CVTTSD2SI : sse12_cvt_s<0x2C, FR64, GR32, fp_to_sint, f64mem, loadf64,
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"cvttsd2si\t{$src, $dst|$dst, $src}">, XD;
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defm CVTSI2SS : sse12_cvt_s<0x2A, GR32, FR32, sint_to_fp, i32mem, loadi32,
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"cvtsi2ss\t{$src, $dst|$dst, $src}">, XS;
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defm CVTSI2SD : sse12_cvt<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32,
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defm CVTSI2SD : sse12_cvt_s<0x2A, GR32, FR64, sint_to_fp, i32mem, loadi32,
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"cvtsi2sd\t{$src, $dst|$dst, $src}">, XD;
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multiclass sse12_cvt_sint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
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Intrinsic Int, X86MemOperand x86memop, PatFrag ld_frag,
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string asm> {
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def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
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[(set DstRC:$dst, (Int SrcRC:$src))]>;
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def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
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[(set DstRC:$dst, (Int (ld_frag addr:$src)))]>;
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}
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// Match intrinsics which expect XMM operand(s).
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defm Int_CVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
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f32mem, load, "cvtss2si\t{$src, $dst|$dst, $src}">, XS;
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defm Int_CVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
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f128mem, load, "cvtsd2si\t{$src, $dst|$dst, $src}">, XD;
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// Conversion Instructions Intrinsics - Match intrinsics which expect MM
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// and/or XMM operand(s).
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multiclass sse12_cvt_pint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
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Intrinsic Int, X86MemOperand x86memop, PatFrag ld_frag,
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string asm, Domain d> {
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@ -672,22 +624,14 @@ multiclass sse12_cvt_pint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
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[(set DstRC:$dst, (Int (ld_frag addr:$src)))], d>;
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}
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// Match intrinsics which expect MM and XMM operand(s).
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defm Int_CVTPS2PI : sse12_cvt_pint<0x2D, VR128, VR64, int_x86_sse_cvtps2pi,
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f64mem, load, "cvtps2pi\t{$src, $dst|$dst, $src}",
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SSEPackedSingle>, TB;
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defm Int_CVTPD2PI : sse12_cvt_pint<0x2D, VR128, VR64, int_x86_sse_cvtpd2pi,
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f128mem, memop, "cvtpd2pi\t{$src, $dst|$dst, $src}",
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SSEPackedDouble>, TB, OpSize;
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// Match intrinsics which expect MM and XMM operand(s).
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defm Int_CVTTPS2PI : sse12_cvt_pint<0x2C, VR128, VR64, int_x86_sse_cvttps2pi,
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f64mem, load, "cvttps2pi\t{$src, $dst|$dst, $src}",
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SSEPackedSingle>, TB;
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defm Int_CVTTPD2PI : sse12_cvt_pint<0x2C, VR128, VR64, int_x86_sse_cvttpd2pi,
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f128mem, memop, "cvttpd2pi\t{$src, $dst|$dst, $src}",
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SSEPackedDouble>, TB, OpSize;
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multiclass sse12_cvt_sint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
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Intrinsic Int, X86MemOperand x86memop, PatFrag ld_frag,
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string asm> {
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def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
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[(set DstRC:$dst, (Int SrcRC:$src))]>;
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def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src), asm,
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[(set DstRC:$dst, (Int (ld_frag addr:$src)))]>;
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}
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multiclass sse12_cvt_pint_3addr<bits<8> opc, RegisterClass SrcRC,
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RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
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@ -699,15 +643,79 @@ multiclass sse12_cvt_pint_3addr<bits<8> opc, RegisterClass SrcRC,
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[(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))], d>;
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}
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multiclass sse12_cvt_sint_3addr<bits<8> opc, RegisterClass SrcRC,
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RegisterClass DstRC, Intrinsic Int, X86MemOperand x86memop,
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PatFrag ld_frag, string asm> {
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def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src2),
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asm, [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))]>;
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def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
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(ins DstRC:$src1, x86memop:$src2), asm,
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[(set DstRC:$dst, (Int DstRC:$src1, (ld_frag addr:$src2)))]>;
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}
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let Constraints = "$src1 = $dst" in
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let isAsmParserOnly = 1 in {
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defm Int_VCVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
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f32mem, load, "cvtss2si\t{$src, $dst|$dst, $src}">, XS,
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VEX;
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defm Int_VCVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
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f128mem, load, "cvtsd2si\t{$src, $dst|$dst, $src}">, XD,
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VEX;
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}
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defm Int_CVTSS2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse_cvtss2si,
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f32mem, load, "cvtss2si\t{$src, $dst|$dst, $src}">, XS;
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defm Int_CVTSD2SI : sse12_cvt_sint<0x2D, VR128, GR32, int_x86_sse2_cvtsd2si,
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f128mem, load, "cvtsd2si\t{$src, $dst|$dst, $src}">, XD;
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let Constraints = "$src1 = $dst" in {
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defm Int_CVTSI2SS : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
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int_x86_sse_cvtsi2ss, i32mem, loadi32,
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"cvtsi2ss\t{$src2, $dst|$dst, $src2}">, XS;
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defm Int_CVTSI2SD : sse12_cvt_sint_3addr<0x2A, GR32, VR128,
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int_x86_sse2_cvtsi2sd, i32mem, loadi32,
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"cvtsi2ss\t{$src2, $dst|$dst, $src2}">, XD;
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}
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// Instructions below don't have an AVX form.
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defm Int_CVTPS2PI : sse12_cvt_pint<0x2D, VR128, VR64, int_x86_sse_cvtps2pi,
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f64mem, load, "cvtps2pi\t{$src, $dst|$dst, $src}",
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SSEPackedSingle>, TB;
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defm Int_CVTPD2PI : sse12_cvt_pint<0x2D, VR128, VR64, int_x86_sse_cvtpd2pi,
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f128mem, memop, "cvtpd2pi\t{$src, $dst|$dst, $src}",
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SSEPackedDouble>, TB, OpSize;
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defm Int_CVTTPS2PI : sse12_cvt_pint<0x2C, VR128, VR64, int_x86_sse_cvttps2pi,
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f64mem, load, "cvttps2pi\t{$src, $dst|$dst, $src}",
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SSEPackedSingle>, TB;
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defm Int_CVTTPD2PI : sse12_cvt_pint<0x2C, VR128, VR64, int_x86_sse_cvttpd2pi,
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f128mem, memop, "cvttpd2pi\t{$src, $dst|$dst, $src}",
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SSEPackedDouble>, TB, OpSize;
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defm Int_CVTPI2PD : sse12_cvt_pint<0x2A, VR64, VR128, int_x86_sse_cvtpi2pd,
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i64mem, load, "cvtpi2pd\t{$src, $dst|$dst, $src}",
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SSEPackedDouble>, TB, OpSize;
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let Constraints = "$src1 = $dst" in {
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defm Int_CVTPI2PS : sse12_cvt_pint_3addr<0x2A, VR64, VR128,
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int_x86_sse_cvtpi2ps,
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i64mem, load, "cvtpi2ps\t{$src2, $dst|$dst, $src2}",
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SSEPackedSingle>, TB;
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defm Int_CVTPI2PD : sse12_cvt_pint<0x2A, VR64, VR128, int_x86_sse_cvtpi2pd,
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i64mem, load, "cvtpi2pd\t{$src, $dst|$dst, $src}",
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SSEPackedDouble>, TB, OpSize;
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}
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/// SSE 1 Only
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// Aliases for intrinsics
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defm Int_CVTTSS2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse_cvttss2si,
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f32mem, load, "cvttss2si\t{$src, $dst|$dst, $src}">,
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XS;
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defm Int_CVTTSD2SI : sse12_cvt_sint<0x2C, VR128, GR32, int_x86_sse2_cvttsd2si,
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f128mem, load, "cvttss2si\t{$src, $dst|$dst, $src}">,
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XD;
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let Pattern = []<dag> in {
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defm CVTSS2SI : sse12_cvt_s<0x2D, FR32, GR32, undef, f32mem, load /*dummy*/,
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"cvtss2si{l}\t{$src, $dst|$dst, $src}">, XS;
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defm CVTDQ2PS : sse12_cvt_p<0x5B, VR128, VR128, undef, f128mem, load /*dummy*/,
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"cvtdq2ps\t{$src, $dst|$dst, $src}",
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SSEPackedSingle>, TB; /* PD SSE3 form is avaiable */
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}
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//===----------------------------------------------------------------------===//
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// SSE 1 & 2 - Compare Instructions
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@ -1601,16 +1609,6 @@ def : Pat<(extloadf32 addr:$src),
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(CVTSS2SDrr (MOVSSrm addr:$src))>,
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Requires<[HasSSE2, OptForSpeed]>;
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// Aliases for intrinsics
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def Int_CVTTSD2SIrr : SDI<0x2C, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src),
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"cvttsd2si\t{$src, $dst|$dst, $src}",
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[(set GR32:$dst,
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(int_x86_sse2_cvttsd2si VR128:$src))]>;
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def Int_CVTTSD2SIrm : SDI<0x2C, MRMSrcMem, (outs GR32:$dst), (ins f128mem:$src),
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"cvttsd2si\t{$src, $dst|$dst, $src}",
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[(set GR32:$dst, (int_x86_sse2_cvttsd2si
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(load addr:$src)))]>;
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//===---------------------------------------------------------------------===//
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// SSE packed FP Instructions
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@ -1774,16 +1772,6 @@ def Int_CVTPD2PSrm : PDI<0x5A, MRMSrcMem, (outs VR128:$dst), (ins f128mem:$src),
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// Match intrinsics which expect XMM operand(s).
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// Aliases for intrinsics
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let Constraints = "$src1 = $dst" in {
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def Int_CVTSI2SDrr: SDI<0x2A, MRMSrcReg,
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(outs VR128:$dst), (ins VR128:$src1, GR32:$src2),
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"cvtsi2sd\t{$src2, $dst|$dst, $src2}",
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[(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
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GR32:$src2))]>;
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def Int_CVTSI2SDrm: SDI<0x2A, MRMSrcMem,
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(outs VR128:$dst), (ins VR128:$src1, i32mem:$src2),
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"cvtsi2sd\t{$src2, $dst|$dst, $src2}",
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[(set VR128:$dst, (int_x86_sse2_cvtsi2sd VR128:$src1,
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(loadi32 addr:$src2)))]>;
|
||||
def Int_CVTSD2SSrr: SDI<0x5A, MRMSrcReg,
|
||||
(outs VR128:$dst), (ins VR128:$src1, VR128:$src2),
|
||||
"cvtsd2ss\t{$src2, $dst|$dst, $src2}",
|
||||
|
||||
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Reference in New Issue
Block a user