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Remove many calls to TII::isMoveInstr. Targets should be producing COPY anyway.

Browse Source 
TII::isMoveInstr is going tobe completely removed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108507 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen 2010-07-16 04:45:42 +00:00
parent 18c479c600
commit 04c528a0c8
15 changed files with 74 additions and 228 deletions
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8
lib/CodeGen/AsmPrinter/AsmPrinter.cpp
View File

@ -510,12 +510,8 @@ static void EmitComments(const MachineInstr &MI, raw_ostream &CommentOS) {
}
// Check for spill-induced copies
unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
if (TM.getInstrInfo()->isMoveInstr(MI, SrcReg, DstReg,
SrcSubIdx, DstSubIdx)) {
if (MI.getAsmPrinterFlag(MachineInstr::ReloadReuse))
CommentOS << " Reload Reuse\n";
}
if (MI.getAsmPrinterFlag(MachineInstr::ReloadReuse))
CommentOS << " Reload Reuse\n";
}
/// EmitImplicitDef - This method emits the specified machine instruction

20
lib/CodeGen/LiveIntervalAnalysis.cpp
View File

@ -188,10 +188,6 @@ bool LiveIntervals::conflictsWithPhysReg(const LiveInterval &li,
const MachineInstr &MI = *I;
// Allow copies to and from li.reg
unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
if (tii_->isMoveInstr(MI, SrcReg, DstReg, SrcSubReg, DstSubReg))
if (SrcReg == li.reg || DstReg == li.reg)
continue;
if (MI.isCopy())
if (MI.getOperand(0).getReg() == li.reg ||
MI.getOperand(1).getReg() == li.reg)
@ -324,9 +320,7 @@ void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb,
mi->addRegisterDefined(interval.reg);
MachineInstr *CopyMI = NULL;
unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
if (mi->isCopyLike() ||
tii_->isMoveInstr(*mi, SrcReg, DstReg, SrcSubReg, DstSubReg)) {
if (mi->isCopyLike()) {
CopyMI = mi;
}
@ -454,9 +448,7 @@ void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb,
OldValNo->setCopy(0);
// A re-def may be a copy. e.g. %reg1030:6<def> = VMOVD %reg1026, ...
unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
if (PartReDef && (mi->isCopyLike() ||
tii_->isMoveInstr(*mi, SrcReg, DstReg, SrcSubReg, DstSubReg)))
if (PartReDef && mi->isCopyLike())
OldValNo->setCopy(&*mi);
// Add the new live interval which replaces the range for the input copy.
@ -485,9 +477,7 @@ void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb,
VNInfo *ValNo;
MachineInstr *CopyMI = NULL;
unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
if (mi->isCopyLike() ||
tii_->isMoveInstr(*mi, SrcReg, DstReg, SrcSubReg, DstSubReg))
if (mi->isCopyLike())
CopyMI = mi;
ValNo = interval.getNextValue(defIndex, CopyMI, true, VNInfoAllocator);
@ -602,9 +592,7 @@ void LiveIntervals::handleRegisterDef(MachineBasicBlock *MBB,
getOrCreateInterval(MO.getReg()));
else if (allocatableRegs_[MO.getReg()]) {
MachineInstr *CopyMI = NULL;
unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
if (MI->isCopyLike() ||
tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubReg, DstSubReg))
if (MI->isCopyLike())
CopyMI = MI;
handlePhysicalRegisterDef(MBB, MI, MIIdx, MO,
getOrCreateInterval(MO.getReg()), CopyMI);

34
lib/CodeGen/MachineCSE.cpp
View File

@ -107,29 +107,9 @@ bool MachineCSE::PerformTrivialCoalescing(MachineInstr *MI,
MachineInstr *DefMI = MRI->getVRegDef(Reg);
if (DefMI->getParent() != MBB)
continue;
unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
if (TII->isMoveInstr(*DefMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
TargetRegisterInfo::isVirtualRegister(SrcReg) &&
!SrcSubIdx && !DstSubIdx) {
const TargetRegisterClass *SRC = MRI->getRegClass(SrcReg);
const TargetRegisterClass *RC = MRI->getRegClass(Reg);
const TargetRegisterClass *NewRC = getCommonSubClass(RC, SRC);
if (!NewRC)
continue;
DEBUG(dbgs() << "Coalescing: " << *DefMI);
DEBUG(dbgs() << "*** to: " << *MI);
MO.setReg(SrcReg);
MRI->clearKillFlags(SrcReg);
if (NewRC != SRC)
MRI->setRegClass(SrcReg, NewRC);
DefMI->eraseFromParent();
++NumCoalesces;
Changed = true;
}
if (!DefMI->isCopy())
continue;
SrcReg = DefMI->getOperand(1).getReg();
unsigned SrcReg = DefMI->getOperand(1).getReg();
if (!TargetRegisterInfo::isVirtualRegister(SrcReg))
continue;
if (DefMI->getOperand(0).getSubReg() || DefMI->getOperand(1).getSubReg())
@ -261,19 +241,13 @@ bool MachineCSE::PhysRegDefReaches(MachineInstr *CSMI, MachineInstr *MI,
return false;
}
static bool isCopy(const MachineInstr *MI, const TargetInstrInfo *TII) {
unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
return MI->isCopyLike() ||
TII->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx);
}
bool MachineCSE::isCSECandidate(MachineInstr *MI) {
if (MI->isLabel() || MI->isPHI() || MI->isImplicitDef() ||
MI->isKill() || MI->isInlineAsm() || MI->isDebugValue())
return false;
// Ignore copies.
if (isCopy(MI, TII))
if (MI->isCopyLike())
return false;
// Ignore stuff that we obviously can't move.
@ -329,7 +303,7 @@ bool MachineCSE::isProfitableToCSE(unsigned CSReg, unsigned Reg,
E = MRI->use_nodbg_end(); I != E; ++I) {
MachineInstr *Use = &*I;
// Ignore copies.
if (!isCopy(Use, TII)) {
if (!Use->isCopyLike()) {
HasNonCopyUse = true;
break;
}
@ -385,7 +359,7 @@ bool MachineCSE::ProcessBlock(MachineBasicBlock *MBB) {
// Look for trivial copy coalescing opportunities.
if (PerformTrivialCoalescing(MI, MBB)) {
// After coalescing MI itself may become a copy.
if (isCopy(MI, TII))
if (MI->isCopyLike())
continue;
FoundCSE = VNT.count(MI);
}

14
lib/CodeGen/OptimizePHIs.cpp
View File

@ -101,16 +101,10 @@ bool OptimizePHIs::IsSingleValuePHICycle(MachineInstr *MI,
MachineInstr *SrcMI = MRI->getVRegDef(SrcReg);
// Skip over register-to-register moves.
unsigned MvSrcReg, MvDstReg, SrcSubIdx, DstSubIdx;
if (SrcMI &&
TII->isMoveInstr(*SrcMI, MvSrcReg, MvDstReg, SrcSubIdx, DstSubIdx) &&
SrcSubIdx == 0 && DstSubIdx == 0 &&
TargetRegisterInfo::isVirtualRegister(MvSrcReg))
SrcMI = MRI->getVRegDef(MvSrcReg);
else if (SrcMI && SrcMI->isCopy() &&
!SrcMI->getOperand(0).getSubReg() &&
!SrcMI->getOperand(1).getSubReg() &&
TargetRegisterInfo::isVirtualRegister(SrcMI->getOperand(1).getReg()))
if (SrcMI && SrcMI->isCopy() &&
!SrcMI->getOperand(0).getSubReg() &&
!SrcMI->getOperand(1).getSubReg() &&
TargetRegisterInfo::isVirtualRegister(SrcMI->getOperand(1).getReg()))
SrcMI = MRI->getVRegDef(SrcMI->getOperand(1).getReg());
if (!SrcMI)
return false;

6
lib/CodeGen/PreAllocSplitting.cpp
View File

@ -676,11 +676,7 @@ void PreAllocSplitting::ReconstructLiveInterval(LiveInterval* LI) {
VNInfo* NewVN = LI->getNextValue(DefIdx, 0, true, Alloc);
// If the def is a move, set the copy field.
unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
if (TII->isMoveInstr(*DI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)) {
if (DstReg == LI->reg)
NewVN->setCopy(&*DI);
} else if (DI->isCopyLike() && DI->getOperand(0).getReg() == LI->reg)
if (DI->isCopyLike() && DI->getOperand(0).getReg() == LI->reg)
NewVN->setCopy(&*DI);
NewVNs[&*DI] = NewVN;

14
lib/CodeGen/ProcessImplicitDefs.cpp
View File

@ -46,12 +46,6 @@ ProcessImplicitDefs::CanTurnIntoImplicitDef(MachineInstr *MI,
unsigned Reg, unsigned OpIdx,
const TargetInstrInfo *tii_,
SmallSet<unsigned, 8> &ImpDefRegs) {
unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
if (tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubReg, DstSubReg) &&
Reg == SrcReg &&
(DstSubReg == 0 || ImpDefRegs.count(DstReg)))
return true;
switch(OpIdx) {
case 1:
return MI->isCopy() && (MI->getOperand(0).getSubReg() == 0 ||
@ -75,14 +69,6 @@ static bool isUndefCopy(MachineInstr *MI, unsigned Reg,
return true;
return false;
}
unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
if (tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubReg, DstSubReg)) {
if (Reg != SrcReg)
return false;
if (DstSubReg == 0 || ImpDefRegs.count(DstReg))
return true;
}
return false;
}

8
lib/CodeGen/RegAllocFast.cpp
View File

@ -520,12 +520,9 @@ RAFast::defineVirtReg(MachineInstr *MI, unsigned OpNum,
if ((!Hint || !TargetRegisterInfo::isPhysicalRegister(Hint)) &&
MRI->hasOneNonDBGUse(VirtReg)) {
const MachineInstr &UseMI = *MRI->use_nodbg_begin(VirtReg);
unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
// It's a copy, use the destination register as a hint.
if (UseMI.isCopyLike())
Hint = UseMI.getOperand(0).getReg();
else if (TII->isMoveInstr(UseMI, SrcReg, DstReg, SrcSubReg, DstSubReg))
Hint = DstReg;
}
allocVirtReg(MI, *LRI, Hint);
} else if (LR.LastUse) {
@ -789,14 +786,13 @@ void RAFast::AllocateBasicBlock() {
}
// If this is a copy, we may be able to coalesce.
unsigned CopySrc, CopyDst, CopySrcSub, CopyDstSub;
unsigned CopySrc = 0, CopyDst = 0, CopySrcSub = 0, CopyDstSub = 0;
if (MI->isCopy()) {
CopyDst = MI->getOperand(0).getReg();
CopySrc = MI->getOperand(1).getReg();
CopyDstSub = MI->getOperand(0).getSubReg();
CopySrcSub = MI->getOperand(1).getSubReg();
} else if (!TII->isMoveInstr(*MI, CopySrc, CopyDst, CopySrcSub, CopyDstSub))
CopySrc = CopyDst = 0;
}
// Track registers used by instruction.
UsedInInstr.reset();

40
lib/CodeGen/RegAllocLinearScan.cpp
View File

@ -419,20 +419,15 @@ unsigned RALinScan::attemptTrivialCoalescing(LiveInterval &cur, unsigned Reg) {
unsigned CandReg;
{
MachineInstr *CopyMI;
unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
if (vni->def != SlotIndex() && vni->isDefAccurate() &&
(CopyMI = li_->getInstructionFromIndex(vni->def)) &&
(CopyMI->isCopy() ||
tii_->isMoveInstr(*CopyMI, SrcReg, DstReg, SrcSubReg, DstSubReg)))
(CopyMI = li_->getInstructionFromIndex(vni->def)) && CopyMI->isCopy())
// Defined by a copy, try to extend SrcReg forward
CandReg = CopyMI->isCopy() ? CopyMI->getOperand(1).getReg() : SrcReg;
CandReg = CopyMI->getOperand(1).getReg();
else if (TrivCoalesceEnds &&
(CopyMI =
li_->getInstructionFromIndex(range.end.getBaseIndex())) &&
tii_->isMoveInstr(*CopyMI, SrcReg, DstReg, SrcSubReg, DstSubReg) &&
cur.reg == SrcReg)
(CopyMI = li_->getInstructionFromIndex(range.end.getBaseIndex())) &&
CopyMI->isCopy() && cur.reg == CopyMI->getOperand(1).getReg())
// Only used by a copy, try to extend DstReg backwards
CandReg = DstReg;
CandReg = CopyMI->getOperand(0).getReg();
else
return Reg;
}
@ -978,27 +973,10 @@ void RALinScan::assignRegOrStackSlotAtInterval(LiveInterval* cur) {
if ((vni->def != SlotIndex()) && !vni->isUnused() &&
vni->isDefAccurate()) {
MachineInstr *CopyMI = li_->getInstructionFromIndex(vni->def);
unsigned SrcReg, DstReg, SrcSubReg, DstSubReg;
if (CopyMI &&
tii_->isMoveInstr(*CopyMI, SrcReg, DstReg, SrcSubReg, DstSubReg)) {
unsigned Reg = 0;
if (TargetRegisterInfo::isPhysicalRegister(SrcReg))
Reg = SrcReg;
else if (vrm_->isAssignedReg(SrcReg))
Reg = vrm_->getPhys(SrcReg);
if (Reg) {
if (SrcSubReg)
Reg = tri_->getSubReg(Reg, SrcSubReg);
if (DstSubReg)
Reg = tri_->getMatchingSuperReg(Reg, DstSubReg, RC);
if (Reg && allocatableRegs_[Reg] && RC->contains(Reg))
mri_->setRegAllocationHint(cur->reg, 0, Reg);
}
} else if (CopyMI && CopyMI->isCopy()) {
DstReg = CopyMI->getOperand(0).getReg();
DstSubReg = CopyMI->getOperand(0).getSubReg();
SrcReg = CopyMI->getOperand(1).getReg();
SrcSubReg = CopyMI->getOperand(1).getSubReg();
if (CopyMI && CopyMI->isCopy()) {
unsigned DstSubReg = CopyMI->getOperand(0).getSubReg();
unsigned SrcReg = CopyMI->getOperand(1).getReg();
unsigned SrcSubReg = CopyMI->getOperand(1).getSubReg();
unsigned Reg = 0;
if (TargetRegisterInfo::isPhysicalRegister(SrcReg))
Reg = SrcReg;

6
lib/CodeGen/RegAllocPBQP.cpp
View File

@ -379,12 +379,14 @@ PBQPRegAlloc::CoalesceMap PBQPRegAlloc::findCoalesces() {
iItr != iEnd; ++iItr) {
const MachineInstr *instr = &*iItr;
unsigned srcReg, dstReg, srcSubReg, dstSubReg;
// If this isn't a copy then continue to the next instruction.
if (!tii->isMoveInstr(*instr, srcReg, dstReg, srcSubReg, dstSubReg))
if (!instr->isCopy())
continue;
unsigned srcReg = instr->getOperand(1).getReg();
unsigned dstReg = instr->getOperand(0).getReg();
// If the registers are already the same our job is nice and easy.
if (dstReg == srcReg)
continue;

3
lib/CodeGen/RegisterCoalescer.cpp
View File

@ -54,9 +54,8 @@ bool CoalescerPair::isMoveInstr(const MachineInstr *MI,
DstSub = compose(MI->getOperand(0).getSubReg(), MI->getOperand(3).getImm());
Src = MI->getOperand(2).getReg();
SrcSub = MI->getOperand(2).getSubReg();
} else if (!tii_.isMoveInstr(*MI, Src, Dst, SrcSub, DstSub)) {
} else
return false;
}
return true;
}

99
lib/CodeGen/SimpleRegisterCoalescing.cpp
View File

@ -470,16 +470,12 @@ bool SimpleRegisterCoalescing::RemoveCopyByCommutingDef(const CoalescerPair &CP,
if (Extended)
UseMO.setIsKill(false);
}
unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
if (UseMI->isCopy()) {
if (UseMI->getOperand(0).getReg() != IntB.reg ||
UseMI->getOperand(0).getSubReg())
continue;
} else if (tii_->isMoveInstr(*UseMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)){
if (DstReg != IntB.reg || DstSubIdx)
continue;
} else
if (!UseMI->isCopy())
continue;
if (UseMI->getOperand(0).getReg() != IntB.reg ||
UseMI->getOperand(0).getSubReg())
continue;
// This copy will become a noop. If it's defining a new val#,
// remove that val# as well. However this live range is being
// extended to the end of the existing live range defined by the copy.
@ -628,14 +624,6 @@ SimpleRegisterCoalescing::TrimLiveIntervalToLastUse(SlotIndex CopyIdx,
if (DefMO.getReg() == li.reg && !DefMO.getSubReg())
DefMO.setIsDead();
}
unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
if (tii_->isMoveInstr(*LastUseMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
DstReg == li.reg && DstSubIdx == 0) {
// Last use is itself an identity code.
int DeadIdx = LastUseMI->findRegisterDefOperandIdx(li.reg,
false, false, tri_);
LastUseMI->getOperand(DeadIdx).setIsDead();
}
return true;
}
@ -772,16 +760,6 @@ SimpleRegisterCoalescing::UpdateRegDefsUses(const CoalescerPair &CP) {
// A PhysReg copy that won't be coalesced can perhaps be rematerialized
// instead.
if (DstIsPhys) {
unsigned CopySrcReg, CopyDstReg, CopySrcSubIdx, CopyDstSubIdx;
if (tii_->isMoveInstr(*UseMI, CopySrcReg, CopyDstReg,
CopySrcSubIdx, CopyDstSubIdx) &&
CopySrcSubIdx == 0 && CopyDstSubIdx == 0 &&
CopySrcReg != CopyDstReg && CopySrcReg == SrcReg &&
CopyDstReg != DstReg && !JoinedCopies.count(UseMI) &&
ReMaterializeTrivialDef(li_->getInterval(SrcReg), CopyDstReg, 0,
UseMI))
continue;
if (UseMI->isCopy() &&
!UseMI->getOperand(1).getSubReg() &&
!UseMI->getOperand(0).getSubReg() &&
@ -834,28 +812,6 @@ SimpleRegisterCoalescing::UpdateRegDefsUses(const CoalescerPair &CP) {
dbgs() << li_->getInstructionIndex(UseMI) << "\t";
dbgs() << *UseMI;
});
// After updating the operand, check if the machine instruction has
// become a copy. If so, update its val# information.
const TargetInstrDesc &TID = UseMI->getDesc();
if (DstIsPhys || TID.getNumDefs() != 1 || TID.getNumOperands() <= 2)
continue;
unsigned CopySrcReg, CopyDstReg, CopySrcSubIdx, CopyDstSubIdx;
if (tii_->isMoveInstr(*UseMI, CopySrcReg, CopyDstReg,
CopySrcSubIdx, CopyDstSubIdx) &&
CopySrcReg != CopyDstReg &&
(TargetRegisterInfo::isVirtualRegister(CopyDstReg) ||
allocatableRegs_[CopyDstReg])) {
LiveInterval &LI = li_->getInterval(CopyDstReg);
SlotIndex DefIdx =
li_->getInstructionIndex(UseMI).getDefIndex();
if (const LiveRange *DLR = LI.getLiveRangeContaining(DefIdx)) {
if (DLR->valno->def == DefIdx)
DLR->valno->setCopy(UseMI);
}
}
}
}
@ -1543,21 +1499,19 @@ void SimpleRegisterCoalescing::CopyCoalesceInMBB(MachineBasicBlock *MBB,
MachineInstr *Inst = MII++;
// If this isn't a copy nor a extract_subreg, we can't join intervals.
unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
bool isInsUndef = false;
unsigned SrcReg, DstReg;
if (Inst->isCopy()) {
DstReg = Inst->getOperand(0).getReg();
SrcReg = Inst->getOperand(1).getReg();
} else if (Inst->isSubregToReg()) {
DstReg = Inst->getOperand(0).getReg();
SrcReg = Inst->getOperand(2).getReg();
} else if (!tii_->isMoveInstr(*Inst, SrcReg, DstReg, SrcSubIdx, DstSubIdx))
} else
continue;
bool SrcIsPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg);
bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
if (isInsUndef ||
(li_->hasInterval(SrcReg) && li_->getInterval(SrcReg).empty()))
if (li_->hasInterval(SrcReg) && li_->getInterval(SrcReg).empty())
ImpDefCopies.push_back(CopyRec(Inst, 0));
else if (SrcIsPhys || DstIsPhys)
PhysCopies.push_back(CopyRec(Inst, 0));
@ -1679,11 +1633,6 @@ SimpleRegisterCoalescing::lastRegisterUse(SlotIndex Start,
MachineInstr *UseMI = Use.getParent();
if (UseMI->isIdentityCopy())
continue;
unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
if (tii_->isMoveInstr(*UseMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
SrcReg == DstReg && SrcSubIdx == DstSubIdx)
// Ignore identity copies.
continue;
SlotIndex Idx = li_->getInstructionIndex(UseMI);
// FIXME: Should this be Idx != UseIdx? SlotIndex() will return something
// that compares higher than any other interval.
@ -1708,10 +1657,7 @@ SimpleRegisterCoalescing::lastRegisterUse(SlotIndex Start,
return NULL;
// Ignore identity copies.
unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
if (!MI->isIdentityCopy() &&
!(tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
SrcReg == DstReg && SrcSubIdx == DstSubIdx))
if (!MI->isIdentityCopy())
for (unsigned i = 0, NumOps = MI->getNumOperands(); i != NumOps; ++i) {
MachineOperand &Use = MI->getOperand(i);
if (Use.isReg() && Use.isUse() && Use.getReg() &&
@ -1775,21 +1721,19 @@ bool SimpleRegisterCoalescing::runOnMachineFunction(MachineFunction &fn) {
for (MachineBasicBlock::iterator mii = mbb->begin(), mie = mbb->end();
mii != mie; ) {
MachineInstr *MI = mii;
unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
if (JoinedCopies.count(MI)) {
// Delete all coalesced copies.
bool DoDelete = true;
if (!tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)) {
assert(MI->isCopyLike() && "Unrecognized copy instruction");
SrcReg = MI->getOperand(MI->isSubregToReg() ? 2 : 1).getReg();
if (TargetRegisterInfo::isPhysicalRegister(SrcReg))
// Do not delete extract_subreg, insert_subreg of physical
// registers unless the definition is dead. e.g.
// %DO<def> = INSERT_SUBREG %D0<undef>, %S0<kill>, 1
// or else the scavenger may complain. LowerSubregs will
// delete them later.
DoDelete = false;
}
assert(MI->isCopyLike() && "Unrecognized copy instruction");
unsigned SrcReg = MI->getOperand(MI->isSubregToReg() ? 2 : 1).getReg();
if (TargetRegisterInfo::isPhysicalRegister(SrcReg))
// Do not delete extract_subreg, insert_subreg of physical
// registers unless the definition is dead. e.g.
// %DO<def> = INSERT_SUBREG %D0<undef>, %S0<kill>, 1
// or else the scavenger may complain. LowerSubregs will
// delete them later.
DoDelete = false;
if (MI->allDefsAreDead()) {
LiveInterval &li = li_->getInterval(SrcReg);
if (!ShortenDeadCopySrcLiveRange(li, MI))
@ -1840,9 +1784,8 @@ bool SimpleRegisterCoalescing::runOnMachineFunction(MachineFunction &fn) {
}
// If the move will be an identity move delete it
bool isMove= tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx);
if (MI->isIdentityCopy() ||
(isMove && SrcReg == DstReg && SrcSubIdx == DstSubIdx)) {
if (MI->isIdentityCopy()) {
unsigned SrcReg = MI->getOperand(1).getReg();
if (li_->hasInterval(SrcReg)) {
LiveInterval &RegInt = li_->getInterval(SrcReg);
// If def of this move instruction is dead, remove its live range

17
lib/CodeGen/TailDuplication.cpp
View File

@ -254,14 +254,15 @@ bool TailDuplicatePass::TailDuplicateBlocks(MachineFunction &MF) {
// SSA form.
for (unsigned i = 0, e = Copies.size(); i != e; ++i) {
MachineInstr *Copy = Copies[i];
unsigned Src, Dst, SrcSR, DstSR;
if (TII->isMoveInstr(*Copy, Src, Dst, SrcSR, DstSR)) {
MachineRegisterInfo::use_iterator UI = MRI->use_begin(Src);
if (++UI == MRI->use_end()) {
// Copy is the only use. Do trivial copy propagation here.
MRI->replaceRegWith(Dst, Src);
Copy->eraseFromParent();
}
if (!Copy->isCopy())
continue;
unsigned Dst = Copy->getOperand(0).getReg();
unsigned Src = Copy->getOperand(1).getReg();
MachineRegisterInfo::use_iterator UI = MRI->use_begin(Src);
if (++UI == MRI->use_end()) {
// Copy is the only use. Do trivial copy propagation here.
MRI->replaceRegWith(Dst, Src);
Copy->eraseFromParent();
}
}

30
lib/CodeGen/TwoAddressInstructionPass.cpp
View File

@ -380,26 +380,18 @@ static bool isCopyToReg(MachineInstr &MI, const TargetInstrInfo *TII,
bool &IsSrcPhys, bool &IsDstPhys) {
SrcReg = 0;
DstReg = 0;
unsigned SrcSubIdx, DstSubIdx;
if (!TII->isMoveInstr(MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)) {
if (MI.isCopy()) {
DstReg = MI.getOperand(0).getReg();
SrcReg = MI.getOperand(1).getReg();
} else if (MI.isInsertSubreg()) {
DstReg = MI.getOperand(0).getReg();
SrcReg = MI.getOperand(2).getReg();
} else if (MI.isSubregToReg()) {
DstReg = MI.getOperand(0).getReg();
SrcReg = MI.getOperand(2).getReg();
}
}
if (MI.isCopy()) {
DstReg = MI.getOperand(0).getReg();
SrcReg = MI.getOperand(1).getReg();
} else if (MI.isInsertSubreg() || MI.isSubregToReg()) {
DstReg = MI.getOperand(0).getReg();
SrcReg = MI.getOperand(2).getReg();
} else
return false;
if (DstReg) {
IsSrcPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg);
IsDstPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
return true;
}
return false;
IsSrcPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg);
IsDstPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
return true;
}
/// isKilled - Test if the given register value, which is used by the given

1
projects/test-suite Symbolic link
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@ -0,0 +1 @@
../../test-suite

2
test/CodeGen/CellSPU/call_indirect.ll
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@ -12,7 +12,7 @@
; RUN: grep rotqby %t2.s | count 5
; RUN: grep lqd %t2.s | count 13
; RUN: grep ilhu %t2.s | count 2
; RUN: grep ai %t2.s | count 8
; RUN: grep ai %t2.s | count 9
; RUN: grep dispatch_tab %t2.s | count 6
; ModuleID = 'call_indirect.bc'