mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-06-13 04:38:24 +00:00
Remove many calls to TII::isMoveInstr. Targets should be producing COPY anyway.
TII::isMoveInstr is going tobe completely removed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108507 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
@ -470,16 +470,12 @@ bool SimpleRegisterCoalescing::RemoveCopyByCommutingDef(const CoalescerPair &CP,
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if (Extended)
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UseMO.setIsKill(false);
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}
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unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
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if (UseMI->isCopy()) {
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if (UseMI->getOperand(0).getReg() != IntB.reg ||
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UseMI->getOperand(0).getSubReg())
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continue;
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} else if (tii_->isMoveInstr(*UseMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)){
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if (DstReg != IntB.reg || DstSubIdx)
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continue;
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} else
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if (!UseMI->isCopy())
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continue;
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if (UseMI->getOperand(0).getReg() != IntB.reg ||
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UseMI->getOperand(0).getSubReg())
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continue;
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// This copy will become a noop. If it's defining a new val#,
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// remove that val# as well. However this live range is being
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// extended to the end of the existing live range defined by the copy.
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@ -628,14 +624,6 @@ SimpleRegisterCoalescing::TrimLiveIntervalToLastUse(SlotIndex CopyIdx,
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if (DefMO.getReg() == li.reg && !DefMO.getSubReg())
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DefMO.setIsDead();
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}
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unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
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if (tii_->isMoveInstr(*LastUseMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
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DstReg == li.reg && DstSubIdx == 0) {
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// Last use is itself an identity code.
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int DeadIdx = LastUseMI->findRegisterDefOperandIdx(li.reg,
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false, false, tri_);
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LastUseMI->getOperand(DeadIdx).setIsDead();
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}
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return true;
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}
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@ -772,16 +760,6 @@ SimpleRegisterCoalescing::UpdateRegDefsUses(const CoalescerPair &CP) {
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// A PhysReg copy that won't be coalesced can perhaps be rematerialized
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// instead.
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if (DstIsPhys) {
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unsigned CopySrcReg, CopyDstReg, CopySrcSubIdx, CopyDstSubIdx;
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if (tii_->isMoveInstr(*UseMI, CopySrcReg, CopyDstReg,
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CopySrcSubIdx, CopyDstSubIdx) &&
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CopySrcSubIdx == 0 && CopyDstSubIdx == 0 &&
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CopySrcReg != CopyDstReg && CopySrcReg == SrcReg &&
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CopyDstReg != DstReg && !JoinedCopies.count(UseMI) &&
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ReMaterializeTrivialDef(li_->getInterval(SrcReg), CopyDstReg, 0,
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UseMI))
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continue;
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if (UseMI->isCopy() &&
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!UseMI->getOperand(1).getSubReg() &&
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!UseMI->getOperand(0).getSubReg() &&
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@ -834,28 +812,6 @@ SimpleRegisterCoalescing::UpdateRegDefsUses(const CoalescerPair &CP) {
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dbgs() << li_->getInstructionIndex(UseMI) << "\t";
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dbgs() << *UseMI;
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});
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// After updating the operand, check if the machine instruction has
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// become a copy. If so, update its val# information.
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const TargetInstrDesc &TID = UseMI->getDesc();
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if (DstIsPhys || TID.getNumDefs() != 1 || TID.getNumOperands() <= 2)
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continue;
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unsigned CopySrcReg, CopyDstReg, CopySrcSubIdx, CopyDstSubIdx;
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if (tii_->isMoveInstr(*UseMI, CopySrcReg, CopyDstReg,
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CopySrcSubIdx, CopyDstSubIdx) &&
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CopySrcReg != CopyDstReg &&
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(TargetRegisterInfo::isVirtualRegister(CopyDstReg) ||
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allocatableRegs_[CopyDstReg])) {
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LiveInterval &LI = li_->getInterval(CopyDstReg);
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SlotIndex DefIdx =
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li_->getInstructionIndex(UseMI).getDefIndex();
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if (const LiveRange *DLR = LI.getLiveRangeContaining(DefIdx)) {
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if (DLR->valno->def == DefIdx)
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DLR->valno->setCopy(UseMI);
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}
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}
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}
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}
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@ -1543,21 +1499,19 @@ void SimpleRegisterCoalescing::CopyCoalesceInMBB(MachineBasicBlock *MBB,
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MachineInstr *Inst = MII++;
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// If this isn't a copy nor a extract_subreg, we can't join intervals.
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unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
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bool isInsUndef = false;
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unsigned SrcReg, DstReg;
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if (Inst->isCopy()) {
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DstReg = Inst->getOperand(0).getReg();
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SrcReg = Inst->getOperand(1).getReg();
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} else if (Inst->isSubregToReg()) {
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DstReg = Inst->getOperand(0).getReg();
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SrcReg = Inst->getOperand(2).getReg();
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} else if (!tii_->isMoveInstr(*Inst, SrcReg, DstReg, SrcSubIdx, DstSubIdx))
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} else
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continue;
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bool SrcIsPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg);
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bool DstIsPhys = TargetRegisterInfo::isPhysicalRegister(DstReg);
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if (isInsUndef ||
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(li_->hasInterval(SrcReg) && li_->getInterval(SrcReg).empty()))
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if (li_->hasInterval(SrcReg) && li_->getInterval(SrcReg).empty())
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ImpDefCopies.push_back(CopyRec(Inst, 0));
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else if (SrcIsPhys || DstIsPhys)
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PhysCopies.push_back(CopyRec(Inst, 0));
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@ -1679,11 +1633,6 @@ SimpleRegisterCoalescing::lastRegisterUse(SlotIndex Start,
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MachineInstr *UseMI = Use.getParent();
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if (UseMI->isIdentityCopy())
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continue;
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unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
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if (tii_->isMoveInstr(*UseMI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
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SrcReg == DstReg && SrcSubIdx == DstSubIdx)
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// Ignore identity copies.
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continue;
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SlotIndex Idx = li_->getInstructionIndex(UseMI);
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// FIXME: Should this be Idx != UseIdx? SlotIndex() will return something
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// that compares higher than any other interval.
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@ -1708,10 +1657,7 @@ SimpleRegisterCoalescing::lastRegisterUse(SlotIndex Start,
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return NULL;
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// Ignore identity copies.
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unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
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if (!MI->isIdentityCopy() &&
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!(tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx) &&
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SrcReg == DstReg && SrcSubIdx == DstSubIdx))
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if (!MI->isIdentityCopy())
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for (unsigned i = 0, NumOps = MI->getNumOperands(); i != NumOps; ++i) {
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MachineOperand &Use = MI->getOperand(i);
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if (Use.isReg() && Use.isUse() && Use.getReg() &&
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@ -1775,21 +1721,19 @@ bool SimpleRegisterCoalescing::runOnMachineFunction(MachineFunction &fn) {
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for (MachineBasicBlock::iterator mii = mbb->begin(), mie = mbb->end();
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mii != mie; ) {
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MachineInstr *MI = mii;
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unsigned SrcReg, DstReg, SrcSubIdx, DstSubIdx;
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if (JoinedCopies.count(MI)) {
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// Delete all coalesced copies.
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bool DoDelete = true;
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if (!tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx)) {
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assert(MI->isCopyLike() && "Unrecognized copy instruction");
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SrcReg = MI->getOperand(MI->isSubregToReg() ? 2 : 1).getReg();
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if (TargetRegisterInfo::isPhysicalRegister(SrcReg))
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// Do not delete extract_subreg, insert_subreg of physical
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// registers unless the definition is dead. e.g.
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// %DO<def> = INSERT_SUBREG %D0<undef>, %S0<kill>, 1
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// or else the scavenger may complain. LowerSubregs will
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// delete them later.
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DoDelete = false;
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}
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assert(MI->isCopyLike() && "Unrecognized copy instruction");
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unsigned SrcReg = MI->getOperand(MI->isSubregToReg() ? 2 : 1).getReg();
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if (TargetRegisterInfo::isPhysicalRegister(SrcReg))
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// Do not delete extract_subreg, insert_subreg of physical
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// registers unless the definition is dead. e.g.
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// %DO<def> = INSERT_SUBREG %D0<undef>, %S0<kill>, 1
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// or else the scavenger may complain. LowerSubregs will
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// delete them later.
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DoDelete = false;
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if (MI->allDefsAreDead()) {
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LiveInterval &li = li_->getInterval(SrcReg);
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if (!ShortenDeadCopySrcLiveRange(li, MI))
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@ -1840,9 +1784,8 @@ bool SimpleRegisterCoalescing::runOnMachineFunction(MachineFunction &fn) {
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}
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// If the move will be an identity move delete it
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bool isMove= tii_->isMoveInstr(*MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx);
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if (MI->isIdentityCopy() ||
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(isMove && SrcReg == DstReg && SrcSubIdx == DstSubIdx)) {
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if (MI->isIdentityCopy()) {
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unsigned SrcReg = MI->getOperand(1).getReg();
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if (li_->hasInterval(SrcReg)) {
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LiveInterval &RegInt = li_->getInterval(SrcReg);
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// If def of this move instruction is dead, remove its live range
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