mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-02-08 06:32:24 +00:00
Simplify setcc code a bit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4799 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
parent
77875d88d0
commit
05093a51b4
@ -81,7 +81,13 @@ namespace {
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void visitXor(BinaryOperator &B) { visitSimpleBinary(B, 4); }
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// Binary comparison operators
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void visitSetCondInst(SetCondInst &I);
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void visitSetCCInst(SetCondInst &I, unsigned OpNum);
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void visitSetEQ(SetCondInst &I) { visitSetCCInst(I, 0); }
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void visitSetNE(SetCondInst &I) { visitSetCCInst(I, 1); }
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void visitSetLT(SetCondInst &I) { visitSetCCInst(I, 2); }
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void visitSetGT(SetCondInst &I) { visitSetCCInst(I, 3); }
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void visitSetLE(SetCondInst &I) { visitSetCCInst(I, 4); }
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void visitSetGE(SetCondInst &I) { visitSetCCInst(I, 5); }
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// Memory Instructions
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void visitLoadInst(LoadInst &I);
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@ -193,77 +199,52 @@ void ISel::copyConstantToRegister(Constant *C, unsigned R) {
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/// compare-and-pop-twice, and then copying the concodes to the main
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/// processor's concodes (I didn't make this up, it's in the Intel manual)
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///
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void
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ISel::visitSetCondInst (SetCondInst & I)
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{
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void ISel::visitSetCCInst(SetCondInst &I, unsigned OpNum) {
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// The arguments are already supposed to be of the same type.
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Value *var1 = I.getOperand (0);
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Value *var2 = I.getOperand (1);
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unsigned reg1 = getReg (var1);
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unsigned reg2 = getReg (var2);
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unsigned resultReg = getReg (I);
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unsigned comparisonWidth = var1->getType ()->getPrimitiveSize ();
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unsigned unsignedComparison = var1->getType ()->isUnsigned ();
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unsigned resultWidth = I.getType ()->getPrimitiveSize ();
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bool fpComparison = var1->getType ()->isFloatingPoint ();
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if (fpComparison)
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{
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// Push the variables on the stack with fldl opcodes.
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// FIXME: assuming var1, var2 are in memory, if not, spill to
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// stack first
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switch (comparisonWidth)
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{
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case 4:
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BuildMI (BB, X86::FLDr4, 1, X86::NoReg).addReg (reg1);
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break;
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case 8:
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BuildMI (BB, X86::FLDr8, 1, X86::NoReg).addReg (reg1);
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break;
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default:
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visitInstruction (I);
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break;
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}
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switch (comparisonWidth)
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{
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case 4:
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BuildMI (BB, X86::FLDr4, 1, X86::NoReg).addReg (reg2);
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break;
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case 8:
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BuildMI (BB, X86::FLDr8, 1, X86::NoReg).addReg (reg2);
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break;
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default:
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visitInstruction (I);
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break;
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}
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// (Non-trapping) compare and pop twice.
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BuildMI (BB, X86::FUCOMPP, 0);
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// Move fp status word (concodes) to ax.
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BuildMI (BB, X86::FNSTSWr8, 1, X86::AX);
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// Load real concodes from ax.
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BuildMI (BB, X86::SAHF, 1).addReg(X86::AH);
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}
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else
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{ // integer comparison
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// Emit: cmp <var1>, <var2> (do the comparison). We can
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// compare 8-bit with 8-bit, 16-bit with 16-bit, 32-bit with
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// 32-bit.
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switch (comparisonWidth)
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{
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case 1:
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BuildMI (BB, X86::CMPrr8, 2).addReg (reg1).addReg (reg2);
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break;
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case 2:
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BuildMI (BB, X86::CMPrr16, 2).addReg (reg1).addReg (reg2);
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break;
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case 4:
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BuildMI (BB, X86::CMPrr32, 2).addReg (reg1).addReg (reg2);
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break;
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case 8:
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default:
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visitInstruction (I);
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break;
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}
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}
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const Type *CompTy = I.getOperand(0)->getType();
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unsigned reg1 = getReg(I.getOperand(0));
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unsigned reg2 = getReg(I.getOperand(1));
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unsigned Class = getClass(CompTy);
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switch (Class) {
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// Emit: cmp <var1>, <var2> (do the comparison). We can
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// compare 8-bit with 8-bit, 16-bit with 16-bit, 32-bit with
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// 32-bit.
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case cByte:
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BuildMI (BB, X86::CMPrr8, 2).addReg (reg1).addReg (reg2);
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break;
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case cShort:
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BuildMI (BB, X86::CMPrr16, 2).addReg (reg1).addReg (reg2);
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break;
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case cInt:
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BuildMI (BB, X86::CMPrr32, 2).addReg (reg1).addReg (reg2);
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break;
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// Push the variables on the stack with fldl opcodes.
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// FIXME: assuming var1, var2 are in memory, if not, spill to
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// stack first
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case cFloat: // Floats
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BuildMI (BB, X86::FLDr4, 1, X86::NoReg).addReg (reg1);
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BuildMI (BB, X86::FLDr4, 1, X86::NoReg).addReg (reg2);
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break;
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case cDouble: // Doubles
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BuildMI (BB, X86::FLDr8, 1, X86::NoReg).addReg (reg1);
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BuildMI (BB, X86::FLDr8, 1, X86::NoReg).addReg (reg2);
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break;
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case cLong:
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default:
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visitInstruction(I);
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}
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if (CompTy->isFloatingPoint()) {
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// (Non-trapping) compare and pop twice.
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BuildMI (BB, X86::FUCOMPP, 0);
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// Move fp status word (concodes) to ax.
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BuildMI (BB, X86::FNSTSWr8, 1, X86::AX);
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// Load real concodes from ax.
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BuildMI (BB, X86::SAHF, 1).addReg(X86::AH);
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}
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// Emit setOp instruction (extract concode; clobbers ax),
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// using the following mapping:
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// LLVM -> X86 signed X86 unsigned
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@ -274,59 +255,16 @@ ISel::visitSetCondInst (SetCondInst & I)
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// setgt -> setg seta
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// setle -> setle setbe
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// setge -> setge setae
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switch (I.getOpcode ())
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{
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case Instruction::SetEQ:
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BuildMI (BB, X86::SETE, 0, X86::AL);
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break;
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case Instruction::SetGE:
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if (unsignedComparison)
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BuildMI (BB, X86::SETAE, 0, X86::AL);
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else
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BuildMI (BB, X86::SETGE, 0, X86::AL);
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break;
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case Instruction::SetGT:
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if (unsignedComparison)
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BuildMI (BB, X86::SETA, 0, X86::AL);
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else
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BuildMI (BB, X86::SETG, 0, X86::AL);
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break;
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case Instruction::SetLE:
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if (unsignedComparison)
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BuildMI (BB, X86::SETBE, 0, X86::AL);
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else
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BuildMI (BB, X86::SETLE, 0, X86::AL);
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break;
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case Instruction::SetLT:
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if (unsignedComparison)
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BuildMI (BB, X86::SETB, 0, X86::AL);
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else
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BuildMI (BB, X86::SETL, 0, X86::AL);
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break;
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case Instruction::SetNE:
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BuildMI (BB, X86::SETNE, 0, X86::AL);
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break;
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default:
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visitInstruction (I);
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break;
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}
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static const unsigned OpcodeTab[2][6] = {
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{ X86::SETE, X86::SETNE, X86::SETB, X86::SETA, X86::SETBE, X86::SETAE },
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{ X86::SETE, X86::SETNE, X86::SETL, X86::SETG, X86::SETLE, X86::SETGE },
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};
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BuildMI(BB, OpcodeTab[CompTy->isSigned()][OpNum], 0, X86::AL);
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// Put it in the result using a move.
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switch (resultWidth)
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{
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case 1:
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BuildMI (BB, X86::MOVrr8, 1, resultReg).addReg (X86::AL);
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break;
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case 2:
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BuildMI (BB, X86::MOVZXr16r8, 1, resultReg).addReg (X86::AL);
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break;
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case 4:
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BuildMI (BB, X86::MOVZXr32r8, 1, resultReg).addReg (X86::AL);
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break;
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case 8:
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default:
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visitInstruction (I);
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break;
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}
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BuildMI (BB, X86::MOVrr8, 1, getReg(I)).addReg(X86::AL);
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}
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@ -81,7 +81,13 @@ namespace {
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void visitXor(BinaryOperator &B) { visitSimpleBinary(B, 4); }
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// Binary comparison operators
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void visitSetCondInst(SetCondInst &I);
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void visitSetCCInst(SetCondInst &I, unsigned OpNum);
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void visitSetEQ(SetCondInst &I) { visitSetCCInst(I, 0); }
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void visitSetNE(SetCondInst &I) { visitSetCCInst(I, 1); }
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void visitSetLT(SetCondInst &I) { visitSetCCInst(I, 2); }
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void visitSetGT(SetCondInst &I) { visitSetCCInst(I, 3); }
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void visitSetLE(SetCondInst &I) { visitSetCCInst(I, 4); }
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void visitSetGE(SetCondInst &I) { visitSetCCInst(I, 5); }
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// Memory Instructions
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void visitLoadInst(LoadInst &I);
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@ -193,77 +199,52 @@ void ISel::copyConstantToRegister(Constant *C, unsigned R) {
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/// compare-and-pop-twice, and then copying the concodes to the main
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/// processor's concodes (I didn't make this up, it's in the Intel manual)
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///
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void
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ISel::visitSetCondInst (SetCondInst & I)
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{
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void ISel::visitSetCCInst(SetCondInst &I, unsigned OpNum) {
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// The arguments are already supposed to be of the same type.
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Value *var1 = I.getOperand (0);
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Value *var2 = I.getOperand (1);
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unsigned reg1 = getReg (var1);
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unsigned reg2 = getReg (var2);
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unsigned resultReg = getReg (I);
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unsigned comparisonWidth = var1->getType ()->getPrimitiveSize ();
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unsigned unsignedComparison = var1->getType ()->isUnsigned ();
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unsigned resultWidth = I.getType ()->getPrimitiveSize ();
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bool fpComparison = var1->getType ()->isFloatingPoint ();
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if (fpComparison)
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{
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// Push the variables on the stack with fldl opcodes.
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// FIXME: assuming var1, var2 are in memory, if not, spill to
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// stack first
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switch (comparisonWidth)
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{
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case 4:
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BuildMI (BB, X86::FLDr4, 1, X86::NoReg).addReg (reg1);
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break;
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case 8:
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BuildMI (BB, X86::FLDr8, 1, X86::NoReg).addReg (reg1);
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break;
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default:
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visitInstruction (I);
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break;
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}
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switch (comparisonWidth)
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{
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case 4:
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BuildMI (BB, X86::FLDr4, 1, X86::NoReg).addReg (reg2);
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break;
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case 8:
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BuildMI (BB, X86::FLDr8, 1, X86::NoReg).addReg (reg2);
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break;
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default:
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visitInstruction (I);
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break;
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}
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// (Non-trapping) compare and pop twice.
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BuildMI (BB, X86::FUCOMPP, 0);
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// Move fp status word (concodes) to ax.
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BuildMI (BB, X86::FNSTSWr8, 1, X86::AX);
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// Load real concodes from ax.
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BuildMI (BB, X86::SAHF, 1).addReg(X86::AH);
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}
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else
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{ // integer comparison
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// Emit: cmp <var1>, <var2> (do the comparison). We can
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// compare 8-bit with 8-bit, 16-bit with 16-bit, 32-bit with
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// 32-bit.
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switch (comparisonWidth)
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{
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case 1:
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BuildMI (BB, X86::CMPrr8, 2).addReg (reg1).addReg (reg2);
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break;
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case 2:
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BuildMI (BB, X86::CMPrr16, 2).addReg (reg1).addReg (reg2);
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break;
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case 4:
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BuildMI (BB, X86::CMPrr32, 2).addReg (reg1).addReg (reg2);
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break;
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case 8:
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default:
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visitInstruction (I);
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break;
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}
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}
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const Type *CompTy = I.getOperand(0)->getType();
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unsigned reg1 = getReg(I.getOperand(0));
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unsigned reg2 = getReg(I.getOperand(1));
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unsigned Class = getClass(CompTy);
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switch (Class) {
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// Emit: cmp <var1>, <var2> (do the comparison). We can
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// compare 8-bit with 8-bit, 16-bit with 16-bit, 32-bit with
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// 32-bit.
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case cByte:
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BuildMI (BB, X86::CMPrr8, 2).addReg (reg1).addReg (reg2);
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break;
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case cShort:
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BuildMI (BB, X86::CMPrr16, 2).addReg (reg1).addReg (reg2);
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break;
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case cInt:
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BuildMI (BB, X86::CMPrr32, 2).addReg (reg1).addReg (reg2);
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break;
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// Push the variables on the stack with fldl opcodes.
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// FIXME: assuming var1, var2 are in memory, if not, spill to
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// stack first
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case cFloat: // Floats
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BuildMI (BB, X86::FLDr4, 1, X86::NoReg).addReg (reg1);
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BuildMI (BB, X86::FLDr4, 1, X86::NoReg).addReg (reg2);
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break;
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case cDouble: // Doubles
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BuildMI (BB, X86::FLDr8, 1, X86::NoReg).addReg (reg1);
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BuildMI (BB, X86::FLDr8, 1, X86::NoReg).addReg (reg2);
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break;
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case cLong:
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default:
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visitInstruction(I);
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}
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if (CompTy->isFloatingPoint()) {
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// (Non-trapping) compare and pop twice.
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BuildMI (BB, X86::FUCOMPP, 0);
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// Move fp status word (concodes) to ax.
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BuildMI (BB, X86::FNSTSWr8, 1, X86::AX);
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// Load real concodes from ax.
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BuildMI (BB, X86::SAHF, 1).addReg(X86::AH);
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}
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// Emit setOp instruction (extract concode; clobbers ax),
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// using the following mapping:
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// LLVM -> X86 signed X86 unsigned
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@ -274,59 +255,16 @@ ISel::visitSetCondInst (SetCondInst & I)
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// setgt -> setg seta
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// setle -> setle setbe
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// setge -> setge setae
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switch (I.getOpcode ())
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{
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case Instruction::SetEQ:
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BuildMI (BB, X86::SETE, 0, X86::AL);
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break;
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case Instruction::SetGE:
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if (unsignedComparison)
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BuildMI (BB, X86::SETAE, 0, X86::AL);
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else
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BuildMI (BB, X86::SETGE, 0, X86::AL);
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break;
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case Instruction::SetGT:
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if (unsignedComparison)
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BuildMI (BB, X86::SETA, 0, X86::AL);
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else
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BuildMI (BB, X86::SETG, 0, X86::AL);
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break;
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case Instruction::SetLE:
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if (unsignedComparison)
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BuildMI (BB, X86::SETBE, 0, X86::AL);
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else
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BuildMI (BB, X86::SETLE, 0, X86::AL);
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break;
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case Instruction::SetLT:
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if (unsignedComparison)
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BuildMI (BB, X86::SETB, 0, X86::AL);
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else
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BuildMI (BB, X86::SETL, 0, X86::AL);
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break;
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case Instruction::SetNE:
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BuildMI (BB, X86::SETNE, 0, X86::AL);
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break;
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default:
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visitInstruction (I);
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break;
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}
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static const unsigned OpcodeTab[2][6] = {
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{ X86::SETE, X86::SETNE, X86::SETB, X86::SETA, X86::SETBE, X86::SETAE },
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{ X86::SETE, X86::SETNE, X86::SETL, X86::SETG, X86::SETLE, X86::SETGE },
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};
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BuildMI(BB, OpcodeTab[CompTy->isSigned()][OpNum], 0, X86::AL);
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// Put it in the result using a move.
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switch (resultWidth)
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{
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case 1:
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BuildMI (BB, X86::MOVrr8, 1, resultReg).addReg (X86::AL);
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break;
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case 2:
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BuildMI (BB, X86::MOVZXr16r8, 1, resultReg).addReg (X86::AL);
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break;
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case 4:
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BuildMI (BB, X86::MOVZXr32r8, 1, resultReg).addReg (X86::AL);
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break;
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case 8:
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default:
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visitInstruction (I);
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break;
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}
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BuildMI (BB, X86::MOVrr8, 1, getReg(I)).addReg(X86::AL);
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}
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