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Handle bitconverts
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76042 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -129,6 +129,10 @@ SystemZTargetLowering::SystemZTargetLowering(SystemZTargetMachine &tm) :
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setOperationAction(ISD::FCOS, MVT::f32, Expand);
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setOperationAction(ISD::FCOS, MVT::f64, Expand);
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// We have only 64-bit bitconverts
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setOperationAction(ISD::BIT_CONVERT, MVT::f32, Promote);
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setOperationAction(ISD::BIT_CONVERT, MVT::i32, Promote);
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setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
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setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
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setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
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@ -295,6 +295,13 @@ def FCONVGR64 : Pseudo<(outs GR64:$dst), (ins FP64:$src),
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(implicit PSW)]>;
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} // Defs = [PSW]
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def FBCONVG64 : Pseudo<(outs GR64:$dst), (ins FP64:$src),
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"lgdr\t{$dst, $src}",
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[(set GR64:$dst, (bitconvert FP64:$src))]>;
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def FBCONVF64 : Pseudo<(outs FP64:$dst), (ins GR64:$src),
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"ldgr\t{$dst, $src}",
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[(set FP64:$dst, (bitconvert GR64:$src))]>;
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//===----------------------------------------------------------------------===//
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// Test instructions (like AND but do not produce any result)
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@ -785,7 +785,11 @@ def : Pat<(SystemZcall (i64 texternalsym:$dst)), (CALLi texternalsym:$dst)>;
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// FIXME: use add/sub tricks with 32678/-32768
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// Arbitrary immediate support. Implement in terms of LLIHF/OILF.
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// Arbitrary immediate support.
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def : Pat<(i32 imm:$src),
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(EXTRACT_SUBREG (MOV64ri32 (i64 imm:$src)), subreg_32bit)>;
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// Implement in terms of LLIHF/OILF.
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def : Pat<(i64 imm:$imm),
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(OR64rilo32 (MOV64rihi32 (HI32 imm:$imm)), (LO32 imm:$imm))>;
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@ -821,6 +825,3 @@ def : Pat<(mulhu GR64:$src1, GR64:$src2),
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GR64:$src1, subreg_odd),
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GR64:$src2),
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subreg_even)>;
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def : Pat<(i32 imm:$src),
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(EXTRACT_SUBREG (MOV64ri32 (i64 imm:$src)), subreg_32bit)>;
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