mirror of
https://github.com/c64scene-ar/llvm-6502.git
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Revert 56176. All those instruction formats are still needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56180 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
parent
55375a44f9
commit
05fc966401
@ -343,7 +343,8 @@ unsigned ARMCodeEmitter::getAddrMode1SBit(const MachineInstr &MI,
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unsigned ARMCodeEmitter::getAddrMode1InstrBinary(const MachineInstr &MI,
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const TargetInstrDesc &TID,
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unsigned Binary) {
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if ((TID.TSFlags & ARMII::FormMask) == ARMII::Pseudo)
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unsigned Format = TID.TSFlags & ARMII::FormMask;
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if (Format == ARMII::Pseudo)
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abort(); // FIXME
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// Encode S bit if MI modifies CPSR.
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@ -358,7 +359,14 @@ unsigned ARMCodeEmitter::getAddrMode1InstrBinary(const MachineInstr &MI,
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}
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// Encode first non-shifter register operand if ther is one.
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if ((TID.TSFlags & ARMII::FormMask) != ARMII::UnaryFrm) {
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bool isUnary = (Format == ARMII::DPRdMisc ||
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Format == ARMII::DPRdIm ||
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Format == ARMII::DPRdReg ||
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Format == ARMII::DPRdSoReg ||
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Format == ARMII::DPRnIm ||
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Format == ARMII::DPRnReg ||
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Format == ARMII::DPRnSoReg);
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if (!isUnary) {
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Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
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++OpIdx;
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}
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@ -28,15 +28,26 @@ def MulSMUL : Format<6>;
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def Branch : Format<7>;
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def BranchMisc : Format<8>;
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def UnaryFrm : Format<9>;
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def BinaryFrm : Format<10>;
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def DPRdIm : Format<9>;
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def DPRdReg : Format<10>;
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def DPRdSoReg : Format<11>;
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def DPRdMisc : Format<12>;
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def DPRnIm : Format<13>;
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def DPRnReg : Format<14>;
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def DPRnSoReg : Format<15>;
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def DPRIm : Format<16>;
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def DPRReg : Format<17>;
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def DPRSoReg : Format<18>;
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def DPRImS : Format<19>;
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def DPRRegS : Format<20>;
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def DPRSoRegS : Format<21>;
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def LdFrm : Format<11>;
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def StFrm : Format<12>;
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def LdFrm : Format<22>;
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def StFrm : Format<23>;
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def ArithMisc : Format<13>;
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def ThumbFrm : Format<14>;
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def VFPFrm : Format<15>;
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def ArithMisc : Format<24>;
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def ThumbFrm : Format<25>;
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def VFPFrm : Format<26>;
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//===----------------------------------------------------------------------===//
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@ -82,21 +82,35 @@ namespace ARMII {
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BranchMisc = 8 << FormShift,
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// Data Processing instructions
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UnaryFrm = 9 << FormShift,
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BinaryFrm = 10 << FormShift,
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DPRdIm = 9 << FormShift,
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DPRdReg = 10 << FormShift,
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DPRdSoReg = 11 << FormShift,
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DPRdMisc = 12 << FormShift,
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DPRnIm = 13 << FormShift,
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DPRnReg = 14 << FormShift,
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DPRnSoReg = 15 << FormShift,
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DPRIm = 16 << FormShift,
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DPRReg = 17 << FormShift,
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DPRSoReg = 18 << FormShift,
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DPRImS = 19 << FormShift,
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DPRRegS = 20 << FormShift,
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DPRSoRegS = 21 << FormShift,
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// Load and Store
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LdFrm = 11 << FormShift,
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StFrm = 12 << FormShift,
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LdFrm = 22 << FormShift,
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StFrm = 23 << FormShift,
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// Miscellaneous arithmetic instructions
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ArithMisc = 13 << FormShift,
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ArithMisc = 24 << FormShift,
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// Thumb format
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ThumbFrm = 14 << FormShift,
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ThumbFrm = 25 << FormShift,
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// VFP format
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VPFFrm = 15 << FormShift,
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VPFFrm = 26 << FormShift,
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// Field shifts - such shifts are used to set field while generating
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// machine instructions.
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@ -104,8 +118,10 @@ namespace ARMII {
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RegRsShift = 8,
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RegRdShift = 12,
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RegRnShift = 16,
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L_BitShift = 20,
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S_BitShift = 20,
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U_BitShift = 23,
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IndexShift = 24,
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I_BitShift = 25
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};
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}
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@ -344,13 +344,13 @@ include "ARMInstrFormats.td"
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/// AsI1_bin_irs - Defines a set of (op r, {so_imm|r|so_reg}) patterns for a
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/// binop that produces a value.
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multiclass AsI1_bin_irs<bits<4> opcod, string opc, PatFrag opnode> {
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def ri : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), BinaryFrm,
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def ri : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPRIm,
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opc, " $dst, $a, $b",
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[(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>;
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def rr : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), BinaryFrm,
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def rr : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), DPRReg,
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opc, " $dst, $a, $b",
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[(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>;
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def rs : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), BinaryFrm,
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def rs : AsI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPRSoReg,
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opc, " $dst, $a, $b",
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[(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>;
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}
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@ -359,13 +359,13 @@ multiclass AsI1_bin_irs<bits<4> opcod, string opc, PatFrag opnode> {
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/// instruction modifies the CSPR register.
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let Defs = [CPSR] in {
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multiclass ASI1_bin_s_irs<bits<4> opcod, string opc, PatFrag opnode> {
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def ri : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), BinaryFrm,
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def ri : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPRImS,
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opc, "s $dst, $a, $b",
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[(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>;
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def rr : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), BinaryFrm,
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def rr : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b), DPRRegS,
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opc, "s $dst, $a, $b",
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[(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>;
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def rs : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), BinaryFrm,
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def rs : AI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPRSoRegS,
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opc, "s $dst, $a, $b",
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[(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>;
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}
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@ -376,13 +376,13 @@ multiclass ASI1_bin_s_irs<bits<4> opcod, string opc, PatFrag opnode> {
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/// a explicit result, only implicitly set CPSR.
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let Defs = [CPSR] in {
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multiclass AI1_cmp_irs<bits<4> opcod, string opc, PatFrag opnode> {
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def ri : AI1<opcod, (outs), (ins GPR:$a, so_imm:$b), UnaryFrm,
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def ri : AI1<opcod, (outs), (ins GPR:$a, so_imm:$b), DPRnIm,
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opc, " $a, $b",
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[(opnode GPR:$a, so_imm:$b)]>;
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def rr : AI1<opcod, (outs), (ins GPR:$a, GPR:$b), UnaryFrm,
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def rr : AI1<opcod, (outs), (ins GPR:$a, GPR:$b), DPRnReg,
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opc, " $a, $b",
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[(opnode GPR:$a, GPR:$b)]>;
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def rs : AI1<opcod, (outs), (ins GPR:$a, so_reg:$b), UnaryFrm,
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def rs : AI1<opcod, (outs), (ins GPR:$a, so_reg:$b), DPRnSoReg,
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opc, " $a, $b",
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[(opnode GPR:$a, so_reg:$b)]>;
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}
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@ -419,13 +419,13 @@ multiclass AI_bin_rrot<bits<4> opcod, string opc, PatFrag opnode> {
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let Uses = [CPSR] in {
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multiclass AsXI1_bin_c_irs<bits<4> opcod, string opc, PatFrag opnode> {
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def ri : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_imm:$b, cc_out:$s),
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BinaryFrm, !strconcat(opc, "${s} $dst, $a, $b"),
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DPRIm, !strconcat(opc, "${s} $dst, $a, $b"),
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[(set GPR:$dst, (opnode GPR:$a, so_imm:$b))]>;
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def rr : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, GPR:$b, cc_out:$s),
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BinaryFrm, !strconcat(opc, "${s} $dst, $a, $b"),
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DPRReg, !strconcat(opc, "${s} $dst, $a, $b"),
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[(set GPR:$dst, (opnode GPR:$a, GPR:$b))]>;
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def rs : AXI1<opcod, (outs GPR:$dst), (ins GPR:$a, so_reg:$b, cc_out:$s),
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BinaryFrm, !strconcat(opc, "${s} $dst, $a, $b"),
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DPRSoReg, !strconcat(opc, "${s} $dst, $a, $b"),
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[(set GPR:$dst, (opnode GPR:$a, so_reg:$b))]>;
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}
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}
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@ -743,16 +743,16 @@ def STM : AXI4st<0x0, (outs),
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// Move Instructions.
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//
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def MOVr : AsI1<0xD, (outs GPR:$dst), (ins GPR:$src), UnaryFrm,
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def MOVr : AsI1<0xD, (outs GPR:$dst), (ins GPR:$src), DPRdReg,
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"mov", " $dst, $src", []>;
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def MOVs : AsI1<0xD, (outs GPR:$dst), (ins so_reg:$src), UnaryFrm,
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def MOVs : AsI1<0xD, (outs GPR:$dst), (ins so_reg:$src), DPRdSoReg,
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"mov", " $dst, $src", [(set GPR:$dst, so_reg:$src)]>;
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let isReMaterializable = 1 in
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def MOVi : AsI1<0xD, (outs GPR:$dst), (ins so_imm:$src), UnaryFrm,
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def MOVi : AsI1<0xD, (outs GPR:$dst), (ins so_imm:$src), DPRdIm,
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"mov", " $dst, $src", [(set GPR:$dst, so_imm:$src)]>;
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def MOVrx : AsI1<0xD, (outs GPR:$dst), (ins GPR:$src), UnaryFrm,
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def MOVrx : AsI1<0xD, (outs GPR:$dst), (ins GPR:$src), DPRdMisc,
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"mov", " $dst, $src, rrx",
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[(set GPR:$dst, (ARMrrx GPR:$src))]>;
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@ -760,10 +760,10 @@ def MOVrx : AsI1<0xD, (outs GPR:$dst), (ins GPR:$src), UnaryFrm,
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// due to flag operands.
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let Defs = [CPSR] in {
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def MOVsrl_flag : AI1<0xD, (outs GPR:$dst), (ins GPR:$src), UnaryFrm,
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def MOVsrl_flag : AI1<0xD, (outs GPR:$dst), (ins GPR:$src), DPRdMisc,
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"mov", "s $dst, $src, lsr #1",
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[(set GPR:$dst, (ARMsrl_flag GPR:$src))]>;
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def MOVsra_flag : AI1<0xD, (outs GPR:$dst), (ins GPR:$src), UnaryFrm,
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def MOVsra_flag : AI1<0xD, (outs GPR:$dst), (ins GPR:$src), DPRdMisc,
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"mov", "s $dst, $src, asr #1",
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[(set GPR:$dst, (ARMsra_flag GPR:$src))]>;
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}
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@ -823,20 +823,20 @@ defm ADC : AsXI1_bin_c_irs<0x5, "adc", BinOpFrag<(adde node:$LHS, node:$RHS)>>;
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defm SBC : AsXI1_bin_c_irs<0x6, "sbc", BinOpFrag<(sube node:$LHS, node:$RHS)>>;
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// These don't define reg/reg forms, because they are handled above.
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def RSBri : AsI1<0x3, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), BinaryFrm,
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def RSBri : AsI1<0x3, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPRIm,
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"rsb", " $dst, $a, $b",
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[(set GPR:$dst, (sub so_imm:$b, GPR:$a))]>;
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def RSBrs : AsI1<0x3, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), BinaryFrm,
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def RSBrs : AsI1<0x3, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPRSoReg,
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"rsb", " $dst, $a, $b",
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[(set GPR:$dst, (sub so_reg:$b, GPR:$a))]>;
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// RSB with 's' bit set.
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let Defs = [CPSR] in {
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def RSBSri : AI1<0x3, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), BinaryFrm,
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def RSBSri : AI1<0x3, (outs GPR:$dst), (ins GPR:$a, so_imm:$b), DPRIm,
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"rsb", "s $dst, $a, $b",
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[(set GPR:$dst, (subc so_imm:$b, GPR:$a))]>;
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def RSBSrs : AI1<0x3, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), BinaryFrm,
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def RSBSrs : AI1<0x3, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), DPRSoReg,
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"rsb", "s $dst, $a, $b",
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[(set GPR:$dst, (subc so_reg:$b, GPR:$a))]>;
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}
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@ -844,10 +844,10 @@ def RSBSrs : AI1<0x3, (outs GPR:$dst), (ins GPR:$a, so_reg:$b), BinaryFrm,
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// FIXME: Do not allow RSC to be predicated for now. But they can set CPSR.
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let Uses = [CPSR] in {
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def RSCri : AXI1<0x7, (outs GPR:$dst), (ins GPR:$a, so_imm:$b, cc_out:$s),
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BinaryFrm, "rsc${s} $dst, $a, $b",
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DPRIm, "rsc${s} $dst, $a, $b",
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[(set GPR:$dst, (sube so_imm:$b, GPR:$a))]>;
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def RSCrs : AXI1<0x7, (outs GPR:$dst), (ins GPR:$a, so_reg:$b, cc_out:$s),
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BinaryFrm, "rsc${s} $dst, $a, $b",
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DPRSoReg, "rsc${s} $dst, $a, $b",
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[(set GPR:$dst, (sube so_reg:$b, GPR:$a))]>;
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}
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@ -876,12 +876,12 @@ defm ORR : AsI1_bin_irs<0xC, "orr", BinOpFrag<(or node:$LHS, node:$RHS)>>;
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defm EOR : AsI1_bin_irs<0x1, "eor", BinOpFrag<(xor node:$LHS, node:$RHS)>>;
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defm BIC : AsI1_bin_irs<0xE, "bic", BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
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def MVNr : AsI1<0xE, (outs GPR:$dst), (ins GPR:$src), UnaryFrm,
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def MVNr : AsI1<0xE, (outs GPR:$dst), (ins GPR:$src), DPRdReg,
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"mvn", " $dst, $src", [(set GPR:$dst, (not GPR:$src))]>;
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def MVNs : AsI1<0xE, (outs GPR:$dst), (ins so_reg:$src), UnaryFrm,
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def MVNs : AsI1<0xE, (outs GPR:$dst), (ins so_reg:$src), DPRdSoReg,
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"mvn", " $dst, $src", [(set GPR:$dst, (not so_reg:$src))]>;
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let isReMaterializable = 1 in
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def MVNi : AsI1<0xE, (outs GPR:$dst), (ins so_imm:$imm), UnaryFrm,
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def MVNi : AsI1<0xE, (outs GPR:$dst), (ins so_imm:$imm), DPRdIm,
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"mvn", " $dst, $imm", [(set GPR:$dst, so_imm_not:$imm)]>;
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def : ARMPat<(and GPR:$src, so_imm_not:$imm),
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@ -1107,17 +1107,17 @@ def : ARMPat<(ARMcmpNZ GPR:$src, so_imm_neg:$imm),
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// FIXME: should be able to write a pattern for ARMcmov, but can't use
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// a two-value operand where a dag node expects two operands. :(
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def MOVCCr : AI<0xD, (outs GPR:$dst), (ins GPR:$false, GPR:$true),
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UnaryFrm, "mov", " $dst, $true",
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DPRdReg, "mov", " $dst, $true",
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[/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc, CCR:$ccr))*/]>,
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RegConstraint<"$false = $dst">;
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def MOVCCs : AI<0xD, (outs GPR:$dst), (ins GPR:$false, so_reg:$true),
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UnaryFrm, "mov", " $dst, $true",
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DPRdSoReg, "mov", " $dst, $true",
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[/*(set GPR:$dst, (ARMcmov GPR:$false, so_reg:$true, imm:$cc, CCR:$ccr))*/]>,
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RegConstraint<"$false = $dst">;
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def MOVCCi : AI<0xD, (outs GPR:$dst), (ins GPR:$false, so_imm:$true),
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UnaryFrm, "mov", " $dst, $true",
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DPRdIm, "mov", " $dst, $true",
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[/*(set GPR:$dst, (ARMcmov GPR:$false, so_imm:$true, imm:$cc, CCR:$ccr))*/]>,
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RegConstraint<"$false = $dst">;
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@ -1165,7 +1165,7 @@ def : ARMPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
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// Two piece so_imms.
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let isReMaterializable = 1 in
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def MOVi2pieces : AI1x2<0x0, (outs GPR:$dst), (ins so_imm2part:$src), Pseudo,
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def MOVi2pieces : AI1x2<0x0, (outs GPR:$dst), (ins so_imm2part:$src), DPRdMisc,
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"mov", " $dst, $src",
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[(set GPR:$dst, so_imm2part:$src)]>;
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