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Hide some redundant AVX512 instructions from the asm parser, but force them to show up in the disassembler.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@226155 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper 2015-01-15 09:37:15 +00:00
parent dc67d7678a
commit 06185e7f6b
1 changed files with 1 additions and 1 deletions
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lib/Target/X86/X86InstrAVX512.td
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@ -2113,7 +2113,7 @@ multiclass avx512_load_vl<bits<8> opc, string OpcodeStr, string ld_pat,
multiclass avx512_store<bits<8> opc, string OpcodeStr, PatFrag st_frag, multiclass avx512_store<bits<8> opc, string OpcodeStr, PatFrag st_frag,
ValueType OpVT, RegisterClass KRC, RegisterClass RC, ValueType OpVT, RegisterClass KRC, RegisterClass RC,
X86MemOperand memop, Domain d> { X86MemOperand memop, Domain d> {
let isAsmParserOnly = 1, hasSideEffects = 0 in { let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
def rr_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst), (ins RC:$src), def rr_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst), (ins RC:$src),
!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [], d>, !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [], d>,
EVEX; EVEX;