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Thumb assembly support for SETEND instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135778 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -245,23 +245,13 @@ def tBKPT : T1I<(outs), (ins i32imm:$val), NoItinerary, "bkpt\t$val",
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let Inst{7-0} = val;
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}
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def tSETENDBE : T1I<(outs), (ins), NoItinerary, "setend\tbe",
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[/* For disassembly only; pattern left blank */]>,
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T1Encoding<0b101101> {
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def tSETEND : T1I<(outs), (ins setend_op:$end), NoItinerary, "setend\t$end",
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[]>, T1Encoding<0b101101> {
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bits<1> end;
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// A8.6.156
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let Inst{9-5} = 0b10010;
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let Inst{4} = 1;
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let Inst{3} = 1; // Big-Endian
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let Inst{2-0} = 0b000;
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}
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def tSETENDLE : T1I<(outs), (ins), NoItinerary, "setend\tle",
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[/* For disassembly only; pattern left blank */]>,
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T1Encoding<0b101101> {
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// A8.6.156
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let Inst{9-5} = 0b10010;
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let Inst{4} = 1;
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let Inst{3} = 0; // Little-Endian
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let Inst{3} = end;
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let Inst{2-0} = 0b000;
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}
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@ -798,8 +798,7 @@ static bool DisassembleThumb1PushPop(MCInst &MI, unsigned Opcode, uint32_t insn,
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// tBKPT: imm8
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// tNOP, tSEV, tYIELD, tWFE, tWFI:
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// no operand (except predicate pair)
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// tSETENDBE, tSETENDLE, :
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// no operand
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// tSETEND: i1
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// Others: tRd tRn
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static bool DisassembleThumb1Misc(MCInst &MI, unsigned Opcode, uint32_t insn,
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unsigned short NumOps, unsigned &NumOpsAdded, BO B) {
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@ -860,6 +859,12 @@ static bool DisassembleThumb1Misc(MCInst &MI, unsigned Opcode, uint32_t insn,
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return true;
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}
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if (Opcode == ARM::tSETEND) {
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MI.addOperand(MCOperand::CreateImm(slice(insn, 3, 1)));
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NumOpsAdded = 1;
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return true;
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}
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assert(NumOps >= 2 && OpInfo[0].RegClass == ARM::tGPRRegClassID &&
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(OpInfo[1].RegClass < 0 || OpInfo[1].RegClass==ARM::tGPRRegClassID)
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&& "Expect >=2 operands");
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